hdl-benchmarks

Digital hardware modules & projects (i.e. benchmarks) are used for EDA tools evaluation.

Structure

The project has the following catalog structure:

• epfl - EPFL combinational benchmark suite
• iccad-2015 - ICCAD-2015 CAD Contest benchmark suite
• iscas85 - ISCAS'85 benchmarks
• iscas89 - ISCAS'89 benchmarks
• iwls05 - IWLS'2005 benchmarks
• lgsynth91 - LGSynth'1991 benchmarks
• mcnc - MCNC'91 benchmarks
• quip - Quartus University Interface Program (QUIP) benchmarks
• texas97 - Texas-97 benchmarks
• vcegar - VCEGAR benchmarks
• verilog2smv - Verilog2SMV benchmarks

Benchmarks

The following public benchmarks are updated (several bugs and formatting issues are fixed) and are used in this project:

• EPFL Combinational Benchmark Suite was explained in the paper The EPFL Combinational Benchmark Suite, presented at the International Workshop on Logic Synthesis 2015;

• ICCAD 2015 CAD Contest Benchmark Suite is a test suite for solutions of Large-scale Equivalence Checking and Function Correction problem that took part in the CAD Contest during ICCAD 2015 Conference;

• ISCAS'85 benchmarks was proposed by M. Hansen, H. Yalcin, and J. P. Hayes, at the paper "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering," IEEE Design and Test, vol. 16, no. 3, pp. 72-80, July-Sept. 1999. The current version was published by SPORT Lab, University of Southern California;

• ISCAS'89 benchmarks were distributed on tape to participants of the Special Session on Sequential Test Generation, Int. Symposium on Circuits and Systems, May 1989, and are partially characterized in F. Brglez, D. Bryan, K. Kozminski in "Combinational Profiles of Sequential Benchmark Circuits", Proc. IEEE Int. Symposium on Circuits and Systems, pp. 1929-1934, May 1989. The current version was published by Santosh S Malagi and Maxim Jenihhin;

• IWLS 2005 benchmarks were collected by Christoph Albrecht, Cadence Research Laboratories at Berkeley in June 2005 for the sake of IWLS conference;

• LGSynth'91 benchmarks (sometimes called as IWLS'91) is a collection of examples used in conjunction with the 1991 Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis and the extension of the 1989 Logic Synthesis and Optimization Benchmarks User Guide, that were collected by Petr Fišer, Czech Technical University in Prague;

• MCNC benchmarks were published for Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis, 1991, and were collected by Petr Fišer, Czech Technical University in Prague;

• QUIP benchmarks were developed in Altera (now Intel) company as a part of freely distributed QUIP toolkit;

• Texas-97 Benchmarks were developed at the University of Texas as a part of the formal verification course of Dr. Adnan Aziz;

• VCEGAR Benchmarks were developed at the University of Oxford by the system verification team led by Daniel Kroening as a test suite for the VCEGAR (now EBMC) tool;

• Verilog2SMV Benchmarks were developed at the Bruno Kessler Foundation by a team of researchers as a test suite for the Verilog2SMV tool.

Several benchmarks are included as submodules:

• EPFL benchmarks were developed at École Polytechnique Fédérale de Lausanne and consist of 23 natively combinational circuits designed to challenge modern logic optimization tools. The benchmark suite is divided into arithmetic, random/control and MtM (More than ten Milion gates) parts. Each circuit is distributed in Verilog, VHDL, BLIF and AIGER formats.