Scheduled FIRRTL output format; minor refactoring, config and codestyle fixes

README.md

@@ -218,6 +218,7 @@ The list of arguments for `hls`-mode is presented below:
 * `--config <PATH>`: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section.
 * `--out-sv <PATH>`: *optional* filesystem-path option; used to specify the output SystemVerilog file.
 * `--out-dfcir <PATH>`: *optional* filesystem-path option; used to specify the output DFCIR file.
+* `--out-firrtl <PATH>`: *optional* filesystem-path option; used to specify the output FIRRTL file.
 * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**.
 
 **At least one of the `out-*` options has to be specified.**

config.json

@@ -3,6 +3,8 @@
     "config"         : "",
     "asap_scheduler" : false,
     "lp_scheduler"   : false,
-    "sv_out"         : ""
+    "out_sv"         : "",
+    "out_dfcir"      : "",
+    "out_firrtl"     : ""
   }
 }

src/model/dfcir/CMakeLists.txt

@@ -3,6 +3,6 @@ project(DFCIR LANGUAGES CXX)
 set(CMAKE_CXX_STANDARD 17)
 # TODO: Figure out how to pass Tablegen includes the other way.
 # Issue #15 (https://github.com/ispras/utopia-hls/issues/15).
-include_directories(${MLIR_INCLUDE_DIRS}) 
+include_directories(${MLIR_INCLUDE_DIRS})
 add_subdirectory(include)
 add_subdirectory(lib)

src/model/dfcxx/include/dfcxx/typedefs.h

@@ -63,6 +63,7 @@ enum Scheduler {
 enum class OutputFormatID : uint8_t {
   SystemVerilog = 0,
   DFCIR,
+  FIRRTL,
   // Utility value. Constains the number of elements in the enum.
   COUNT
 };

src/model/dfcxx/includeDev/dfcxx/CMakeLists.txt

@@ -1 +1 @@
-add_subdirectory(IRbuilders)
+add_subdirectory(IRbuilders)

src/model/dfcxx/lib/dfcxx/CMakeLists.txt

@@ -4,6 +4,17 @@ add_subdirectory(typebuilders)
 add_subdirectory(vars)
 add_subdirectory(varbuilders)
 
+## By default LLVM, MLIR and DFCIR are compiled without RTTI, but not DFCxx.
+## So using core Pass functionality from MLIR in converter.cpp causes
+## linker-level errors ("undefined reference to `typeinfo for mlir::Pass'").
+## The following lines explicitly disable RTTI for DFCxx.
+if (${CMAKE_CXX_COMPILER_ID} STREQUAL "MSVC")
+  set(DISABLE_RTTI_FLAG "/GR-")
+else()
+  set(DISABLE_RTTI_FLAG "-fno-rtti")
+endif()
+add_definitions(${DISABLE_RTTI_FLAG})
+
 set(SOURCES
   kernel.cpp
   ${IR_BUILDERS_SOURCES}
@@ -36,6 +47,7 @@ target_include_directories(DFCXX
 
 ## MLIRDFCIR is ensured to be compiled beforehand.
 target_link_libraries(DFCXX
+  PRIVATE $<LINK_ONLY:MLIRPass>
   PRIVATE $<LINK_ONLY:Utopia::MLIRDFCIR>
   PRIVATE $<LINK_ONLY:CIRCTHW>
   PRIVATE $<LINK_ONLY:CIRCTSV>

src/model/dfcxx/lib/dfcxx/IRbuilders/builder.cpp

@@ -6,9 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "dfcxx/IRbuilders/builder.h"
+
 #include "circt/Dialect/FIRRTL/FIRRTLDialect.h"
 #include "circt/Dialect/SV/SVDialect.h"
-#include "dfcxx/IRbuilders/builder.h"
 #include "mlir/Parser/Parser.h"
 
 namespace dfcxx {

src/model/dfcxx/lib/dfcxx/converter.cpp

@@ -9,10 +9,36 @@
 #include "dfcxx/converter.h"
 
 #include "circt/Conversion/Passes.h"
+#include "mlir/Pass/Pass.h"
 #include "mlir/Pass/PassManager.h"
 
+#include <memory>
+
 namespace dfcxx {
 
+class DFCIRDumperPass: public mlir::PassWrapper<DFCIRDumperPass, mlir::OperationPass<mlir::ModuleOp>> {
+private:
+  llvm::raw_fd_ostream *stream;
+
+public:
+  MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(DFCIRDumperPass)
+
+  DFCIRDumperPass() = default;
+
+  DFCIRDumperPass(llvm::raw_fd_ostream *stream) : DFCIRDumperPass() {
+    this->stream = stream;
+  }
+
+  void runOnOperation() override {
+    return getOperation()->print(*stream);
+  }
+
+};
+
+std::unique_ptr<mlir::Pass> createDFCIRDumperPass(llvm::raw_fd_ostream *stream) {
+  return std::make_unique<DFCIRDumperPass>(stream);
+}
+
 DFCIRConverter::DFCIRConverter(const DFLatencyConfig &config) {
   this->config = LatencyConfig();
   for (auto [op, latency]: config) {
@@ -42,6 +68,11 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module,
       break;
   }
 
+  // Dump FIRRTL if the corresponding option is specified.
+  if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(FIRRTL)]) {
+    pm.addPass(createDFCIRDumperPass(stream));
+  }
+
   // Add FIRRTL->SystemVerilog passes if SystemVerilog output option is specified.
   if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SystemVerilog)]) {
     pm.addPass(circt::createLowerFIRRTLToHWPass());

src/options.h

@@ -37,6 +37,7 @@
 #define LP_SCHEDULER_JSON "lp_scheduler"
 #define OUT_SV_JSON "out_sv"
 #define OUT_DFCIR_JSON "out_dfcir"
+#define OUT_FIRRTL_JSON "out_firrtl"
 
 //===----------------------------------------------------------------------===//
 // CLI args/flags definitions
@@ -49,6 +50,7 @@
 #define OUTPUT_GROUP "output"
 #define OUT_SV_ARG CLI_ARG("out-sv")
 #define OUT_DFCIR_ARG CLI_ARG("out-dfcir")
+#define OUT_FIRRTL_ARG CLI_ARG("out-firrtl")
 
 //===----------------------------------------------------------------------===//
 
@@ -185,6 +187,9 @@ struct HlsOptions final : public AppOptions {
     outputGroup->add_option(OUT_DFCIR_ARG,
                             outNames[OUT_FORMAT_ID_INT(DFCIR)],
                             "Path to output unscheduled DFCIR");
+    outputGroup->add_option(OUT_FIRRTL_ARG,
+                            outNames[OUT_FORMAT_ID_INT(FIRRTL)],
+                            "Path to output scheduled FIRRTL");
     outputGroup->require_option();
   }
 
@@ -194,6 +199,7 @@ struct HlsOptions final : public AppOptions {
     get(json, LP_SCHEDULER_JSON,   lpScheduler);
     get(json, OUT_SV_JSON,         outNames[OUT_FORMAT_ID_INT(SystemVerilog)]);
     get(json, OUT_DFCIR_JSON,      outNames[OUT_FORMAT_ID_INT(DFCIR)]);
+    get(json, OUT_FIRRTL_JSON,     outNames[OUT_FORMAT_ID_INT(FIRRTL)]);
   }
 
   std::string latConfigFile;

test/model/dfcxx/CMakeLists.txt

@@ -6,5 +6,6 @@ set(DFCXX_TESTS
   model/dfcxx/addconst.cpp
   model/dfcxx/movingsum.cpp
   model/dfcxx/idct.cpp
+  model/dfcxx/output_formats.cpp
   PARENT_SCOPE
 )

test/model/dfcxx/addconst.cpp

@@ -16,15 +16,15 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, AddConstAddInt2Asap) {
   AddConst kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2}
+    {dfcxx::ADD_INT, 2}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, AddConstAddInt2Linear) {
   AddConst kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2}
+    {dfcxx::ADD_INT, 2}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
-}
+}

test/model/dfcxx/idct.cpp

@@ -16,9 +16,9 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, IdctAsap) {
   IDCT kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 1},
-          {dfcxx::MUL_INT, 3},
-          {dfcxx::SUB_INT, 1}
+    {dfcxx::ADD_INT, 1},
+    {dfcxx::MUL_INT, 3},
+    {dfcxx::SUB_INT, 1}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
@@ -28,9 +28,9 @@ TEST(DFCxx, IdctAsap) {
 // TEST(DFCxx, IdctLinear) {
 //   IDCT kernel;
 //   DFLatencyConfig config = {
-//           {dfcxx::ADD_INT, 1},
-//           {dfcxx::MUL_INT, 3},
-//           {dfcxx::SUB_INT, 1}
+//     {dfcxx::ADD_INT, 1},
+//     {dfcxx::MUL_INT, 3},
+//     {dfcxx::SUB_INT, 1}
 //   };
 //   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 // }

test/model/dfcxx/matrixmul2.cpp

@@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, MatrixMul2AddInt2MulInt3Asap) {
   MatrixMul2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3},
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3},
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, MatrixMul2AddInt2MulInt3Linear) {
   MatrixMul2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 2},
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 2},
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
-}
+}

test/model/dfcxx/movingsum.cpp

@@ -16,31 +16,31 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, MovingSumAddInt2Asap) {
   MovingSum kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2}
+    {dfcxx::ADD_INT, 2}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, MovingSumAddInt2Linear) {
   MovingSum kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2}
+    {dfcxx::ADD_INT, 2}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 }
 
 TEST(DFCxx, MovingSumAddInt8Asap) {
   MovingSum kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 8}
+    {dfcxx::ADD_INT, 8}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, MovingSumAddInt8Linear) {
   MovingSum kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 8}
+    {dfcxx::ADD_INT, 8}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
-}
+}

test/model/dfcxx/muxmul.cpp

@@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, MuxMulAddInt2MulInt3Asap) {
   MuxMul kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, MuxMulAddInt2MulInt3Linear) {
   MuxMul kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 }

test/model/dfcxx/output_formats.cpp

@@ -0,0 +1,24 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the Utopia HLS Project, under the Apache License v2.0
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2021-2024 ISP RAS (http://www.ispras.ru)
+//
+//===----------------------------------------------------------------------===//
+
+#include "polynomial2/polynomial2.h"
+
+#include "gtest/gtest.h"
+
+static const Polynomial2 kernel;
+
+static const DFLatencyConfig config =
+    {{dfcxx::ADD_INT, 2}, {dfcxx::MUL_INT, 3}};
+
+TEST(DFCxxOutputFormats, FIRRTL) {
+  Polynomial2 kernel;
+  DFOutputPaths paths = {
+    {dfcxx::OutputFormatID::FIRRTL, NULLDEVICE}
+  };
+  EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true);
+}

test/model/dfcxx/polynomial2.cpp

@@ -16,35 +16,35 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, Polynomial2AddInt2MulInt3Asap) {
   Polynomial2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) {
   Polynomial2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 }
 
 TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) {
   Polynomial2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 8},
-          {dfcxx::MUL_INT, 15}
+    {dfcxx::ADD_INT, 8},
+    {dfcxx::MUL_INT, 15}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, Polynomial2AddInt8MulInt15Linear) {
   Polynomial2 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 8},
-          {dfcxx::MUL_INT, 15}
+    {dfcxx::ADD_INT, 8},
+    {dfcxx::MUL_INT, 15}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 }

test/model/dfcxx/scalar3.cpp

@@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
 TEST(DFCxx, Scalar3AddInt2MulInt3Asap) {
   Scalar3 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
 }
 
 TEST(DFCxx, Scalar3AddInt2MulInt3Linear) {
   Scalar3 kernel;
   DFLatencyConfig config = {
-          {dfcxx::ADD_INT, 2},
-          {dfcxx::MUL_INT, 3}
+    {dfcxx::ADD_INT, 2},
+    {dfcxx::MUL_INT, 3}
   };
   EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
 }