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Bugfixes #64

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merged 2 commits into from
Sep 28, 2023
Merged

Bugfixes #64

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dd91ab7
libavcenc: fix computations that are resulting in overflow
ram-mohan Sep 28, 2023
50a3551
libavcenc: reset mb qp delta ctxt during cabac encoding
ram-mohan Sep 28, 2023
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9 changes: 7 additions & 2 deletions encoder/ih264e_cabac_encode.c
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Original file line number Diff line number Diff line change
Expand Up @@ -598,8 +598,8 @@ static void ih264e_cabac_enc_mb_qp_delta(WORD8 i1_mb_qp_delta,
u4_bins = 0;
i1_bins_len = 1;
/* calculate ctxtInc, depending on neighbour availability */
u1_ctxt_inc = (!(!(ps_cabac_ctxt->i1_prevps_mb_qp_delta_ctxt)));
ps_cabac_ctxt->i1_prevps_mb_qp_delta_ctxt = i1_mb_qp_delta;
u1_ctxt_inc = (!(!(ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt)));
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = i1_mb_qp_delta;

if (u1_code_num == 0)
{
Expand Down Expand Up @@ -1721,6 +1721,7 @@ IH264E_ERROR_T ih264e_write_islice_mb_cabac(entropy_ctxt_t *ps_ent_ctxt)
*(ps_cabac_ctxt->pu1_left_uv_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_y_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_yuv_dc_csbp) = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;
/* Ending bitstream offset for header in bits */
bitstream_end_offset = GET_NUM_BITS(ps_bitstream);
ps_ent_ctxt->u4_header_bits[0] += bitstream_end_offset
Expand Down Expand Up @@ -1887,6 +1888,7 @@ IH264E_ERROR_T ih264e_write_pslice_mb_cabac(entropy_ctxt_t *ps_ent_ctxt)
*(ps_cabac_ctxt->pu1_left_uv_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_y_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_yuv_dc_csbp) = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;
/* Ending bitstream offset for header in bits */
bitstream_end_offset = GET_NUM_BITS(ps_bitstream);
ps_ent_ctxt->u4_header_bits[0] += bitstream_end_offset
Expand Down Expand Up @@ -2002,6 +2004,7 @@ IH264E_ERROR_T ih264e_write_pslice_mb_cabac(entropy_ctxt_t *ps_ent_ctxt)
*(ps_cabac_ctxt->pu1_left_uv_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_y_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_yuv_dc_csbp) = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;
}
ps_curr_ctxt->u1_intrapred_chroma_mode = 0;
ps_curr_ctxt->u1_cbp = cbp;
Expand Down Expand Up @@ -2195,6 +2198,7 @@ IH264E_ERROR_T ih264e_write_bslice_mb_cabac(entropy_ctxt_t *ps_ent_ctxt)
*(ps_cabac_ctxt->pu1_left_uv_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_y_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_yuv_dc_csbp) = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;
/* Ending bitstream offset for header in bits */
bitstream_end_offset = GET_NUM_BITS(ps_bitstream);
ps_ent_ctxt->u4_header_bits[0] += bitstream_end_offset
Expand Down Expand Up @@ -2390,6 +2394,7 @@ IH264E_ERROR_T ih264e_write_bslice_mb_cabac(entropy_ctxt_t *ps_ent_ctxt)
*(ps_cabac_ctxt->pu1_left_uv_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_y_ac_csbp) = 0;
*(ps_cabac_ctxt->pu1_left_yuv_dc_csbp) = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;
}
ps_curr_ctxt->u1_intrapred_chroma_mode = 0;
ps_curr_ctxt->u1_cbp = cbp;
Expand Down
2 changes: 1 addition & 1 deletion encoder/ih264e_cabac_init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -203,7 +203,7 @@ void ih264e_init_cabac_ctxt(entropy_ctxt_t *ps_ent_ctxt)

ih264e_init_cabac_enc_envirnoment(&ps_cabac_ctxt->s_cab_enc_env);

ps_cabac_ctxt->i1_prevps_mb_qp_delta_ctxt = 0;
ps_cabac_ctxt->i1_prev_mb_qp_delta_ctxt = 0;

if (ISLICE != u1_slice_type)
{
Expand Down
4 changes: 2 additions & 2 deletions encoder/ih264e_cabac_structs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -179,8 +179,8 @@ typedef struct

/* These things need to be updated at each MbLevel */

/* Prev ps_mb_qp_delta_ctxt */
WORD8 i1_prevps_mb_qp_delta_ctxt;
/* prev mb qp delta ctxt */
WORD8 i1_prev_mb_qp_delta_ctxt;

/* Pointer to mb_info_ctxt_t map */
mb_info_ctxt_t *ps_mb_map_ctxt_inc;
Expand Down
8 changes: 5 additions & 3 deletions encoder/irc_rate_control_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,9 @@ void irc_initialise_rate_control(rate_control_api_t *ps_rate_control_api,
UWORD32 u4_tgt_ticks)
{
WORD32 i;
UWORD32 u4_frms_in_delay_prd = (u4_frame_rate * u4_max_delay) / 1000000;
UWORD32 u4_frms_in_delay_prd;

X_PROD_Y_DIV_Z(u4_frame_rate, u4_max_delay, 1000000, u4_frms_in_delay_prd);
ps_rate_control_api->e_rc_type = e_rate_control_type;
ps_rate_control_api->u1_is_mb_level_rc_on = u1_is_mb_level_rc_on;

Expand Down Expand Up @@ -307,8 +309,8 @@ void irc_initialise_rate_control(rate_control_api_t *ps_rate_control_api,

/* Initialize the mb level rate control module */
irc_init_mb_level_rc(ps_rate_control_api->ps_mb_rate_control);
ps_rate_control_api->i4_prev_frm_est_bits = u4_avg_bit_rate * 1000
/ u4_frame_rate;
X_PROD_Y_DIV_Z(u4_avg_bit_rate, 1000, u4_frame_rate,
ps_rate_control_api->i4_prev_frm_est_bits);

ps_rate_control_api->prev_ref_pic_type = I_PIC;
}
Expand Down