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added async reset to oscillator
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KaseyHDL committed Apr 17, 2024
1 parent ab81376 commit b77bc0f
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7 changes: 1 addition & 6 deletions src/constants.vh
Original file line number Diff line number Diff line change
Expand Up @@ -8,24 +8,19 @@ localparam [3:0] CTRL_INPUT_S = 4'b0101;
localparam [3:0] CTRL_INPUT_HOLD_S = 4'b0110;
localparam [3:0] CTRL_WIN_S = 4'b0111;
localparam [3:0] CTRL_LOSE_S = 4'b1000;
// localparam [20:0] MAX_TURN_TIME = 21'hF_FFFF;
localparam [20:0] MAX_TURN_TIME = 21'h0_00FFF;

// timer.v
localparam [1:0] TIMR_IDLE_S = 2'b00;
localparam [1:0] TIMR_COUNT_S = 2'b01;

localparam [20:0] TIMR_MAX_C = 21'h00_00F0;
// localparam [20:0] TIMR_MAX_C = 21'h0F_FFFF;

// `define QUICK_PLAY

`ifdef QUICK_PLAY
localparam [24:0] FIVE_SECOND = 25'hFA;
localparam [24:0] HALF_SECOND = 25'h19;
localparam [24:0] QRTR_SECOND = 25'h0C;
`else // human-time
localparam [24:0] FIVE_SECOND = 25'h000_C350; //10KHz time
localparam [24:0] FIVE_SECOND = 25'h000_C350; //10KHz time
localparam [24:0] HALF_SECOND = 25'h000_1388;
localparam [24:0] QRTR_SECOND = 25'h000_09C4;
`endif
94 changes: 44 additions & 50 deletions src/oscillator.v
Original file line number Diff line number Diff line change
Expand Up @@ -3,67 +3,61 @@
* SPDX-License-Identifier: Apache-2.0
*/

//============================================================================//
// Oscillator
//============================================================================//

`define default_netname none

module oscillator
// #(
// parameter CLK_FREQ = 50_000_000_000
// )
(
module oscillator (
input wire CLK, // Clock - 10KHz
input wire RST_N, // Reset_n - active low
input wire [1:0] NOTE_SEL, // Note selection
output reg AUDIO // Oscillator output
);

//-------------------------------------------------------------------
// note: Hz : Cyc@10Mhz : Cyc@50Mhz
// F#5 : 739.99Hz : 13_514 : 67_568
// A 5 : 880.00Hz : 11_363 : 56_818
// C#6 : 1108.70Hz : 9_020 : 45_098
// E 6 : 1318.50Hz : 7_584 : 37_922
//-------------------------------------------------------------------

// Frequencies in millihertz
// localparam Fs5_f = 739_990;
// localparam A_5_f = 880_000;
// localparam Cs6_f = 1108_700;
// localparam E_6_f = 1318_500;

reg [ 1: 0] current_note; //
reg [13: 0] oscillator_counter; //
reg [13: 0] counter_compares [3:0]; // this seems expensive... optimize?

initial begin
counter_compares[0] = 13_514;
counter_compares[1] = 11_363;
counter_compares[2] = 9_020;
counter_compares[3] = 7_584;
end

//-------------------------------------------------------------------
// Okay so the state machine should never introduce a high frequency
// runt pulse in the square wave generator.
// Only at when toggling the output should a new counter value be loaded.
//-------------------------------------------------------------------

always @(posedge CLK) begin

// Handle reset.
if(!RST_N) begin
AUDIO <= 0;
oscillator_counter <= '0;
current_note <= NOTE_SEL;
//-------------------------------------------------------------------
// note: Hz : Cyc@10Mhz : Cyc@50Mhz
// F#5 : 739.99Hz : 13_514 : 67_568
// A 5 : 880.00Hz : 11_363 : 56_818
// C#6 : 1108.70Hz : 9_020 : 45_098
// E 6 : 1318.50Hz : 7_584 : 37_922
//-------------------------------------------------------------------

// Frequencies in millihertz
// localparam Fs5_f = 739_990;
// localparam A_5_f = 880_000;
// localparam Cs6_f = 1108_700;
// localparam E_6_f = 1318_500;

reg [ 1: 0] current_note; //
reg [13: 0] oscillator_counter; //
reg [13: 0] counter_compares [3:0]; // this seems expensive... optimize?

initial begin
counter_compares[0] = 13_514;
counter_compares[1] = 11_363;
counter_compares[2] = 9_020;
counter_compares[3] = 7_584;
end

else begin
oscillator_counter <= oscillator_counter + 1;
if(oscillator_counter == counter_compares[current_note]) begin
current_note <= NOTE_SEL;
AUDIO <= !AUDIO;
//-------------------------------------------------------------------
// Okay so the state machine should never introduce a high frequency
// runt pulse in the square wave generator.
// Only at when toggling the output should a new counter value be loaded.
//-------------------------------------------------------------------
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
AUDIO <= 0;
oscillator_counter <= 0;
current_note <= NOTE_SEL;
end else begin
oscillator_counter <= oscillator_counter + 1;
if (oscillator_counter == counter_compares[current_note]) begin
current_note <= NOTE_SEL;
AUDIO <= !AUDIO;
end
end
end

end

endmodule : oscillator

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