extend the timer and pass most of 02-interrupt cpu_instrs

jonathanballs · Sep 12, 2024 · 177369e · 177369e
1 parent 1fc3b02
commit 177369e
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Showing 4 changed files with 35 additions and 11 deletions.
diff --git a/src/cpu/mod.rs b/src/cpu/mod.rs
@@ -151,7 +151,7 @@ impl CPU {
         mmu.timer.do_cycles(cycles);
 
         // Handle interrupts
-        if self.ime && !just_set_ei {
+        if (self.ime && !just_set_ei) || matches!(instruction, Instruction::Halt) {
             let return_pc = if matches!(instruction, Instruction::Halt) {
                 self.registers.pc + 1
             } else {

diff --git a/src/main.rs b/src/main.rs
@@ -59,7 +59,6 @@ fn main() {
 
 fn emulator_loop(rom: Vec<u8>, tx: Sender<PPU>, rx: Receiver<(bool, Key)>) {
     let mut gameboy = GameBoy::new(rom);
-    //gameboy.breakpoints.insert(0xC6EC);
 
     ctrlc::set_handler(move || {
         if is_debug_enabled() {

diff --git a/src/mmu/mod.rs b/src/mmu/mod.rs
@@ -116,7 +116,12 @@ impl MMU {
             0xFF04..=0xFF07 => self.timer.write_byte(addr, value),
 
             // Interrupt
-            0xFF0F => self.ppu.vblank_irq = value & 0x1 > 0,
+            0xFF0F => {
+                self.ppu.vblank_irq = value & 0x1 == 0x2;
+                self.ppu.stat_irq = value & 0x2 == 0x2;
+                self.timer.timer_irq = value & 0x4 == 0x4;
+                self.joypad.joypad_irq = value & 0x8 == 0x8;
+            }
 
             // DMA transfer
             0xFF46 => {

diff --git a/src/mmu/timer.rs b/src/mmu/timer.rs
@@ -7,21 +7,22 @@ pub struct Timer {
     div: u8,
     tima: u8,
     tma: u8,
-    tac: u8,
+    step: u32,
 }
 
 impl Timer {
     pub fn new() -> Timer {
         Timer {
-            enabled: true,
-
             timer_irq: false,
             div: 0,
             cycles_since_div: 0,
             cycles_since_tima: 0,
             tima: 0,
             tma: 0,
-            tac: 0,
+
+            // tca
+            step: 256,
+            enabled: false,
         }
     }
 
@@ -35,13 +36,14 @@ impl Timer {
         if self.enabled {
             self.cycles_since_tima += n as u32;
 
-            while self.cycles_since_tima >= 256 {
+            while self.cycles_since_tima >= self.step {
                 self.tima = self.tima.wrapping_add(1);
                 if self.tima == 0 {
                     self.tima = self.tma;
                     self.timer_irq = true
                 }
-                self.cycles_since_tima -= 256;
+
+                self.cycles_since_tima -= self.step;
             }
         }
     }
@@ -51,7 +53,16 @@ impl Timer {
             0xFF04 => self.div,
             0xFF05 => self.tima,
             0xFF06 => self.tma,
-            0xFF07 => self.tac,
+            0xFF07 => {
+                0xF8 | (if self.enabled { 0x4 } else { 0 })
+                    | (match self.step {
+                        16 => 1,
+                        64 => 2,
+                        256 => 3,
+                        _ => 0,
+                    })
+            }
+
             _ => unreachable!(),
         }
     }
@@ -64,7 +75,16 @@ impl Timer {
             // Interrupt registers
             0xFF05 => self.tima = value,
             0xFF06 => self.tma = value,
-            0xFF07 => self.tac = value,
+            0xFF07 => {
+                self.enabled = value & 0x4 != 0;
+                self.step = match value & 0x3 {
+                    1 => 16,
+                    2 => 64,
+                    3 => 256,
+                    _ => 1024,
+                };
+            }
+
             _ => unreachable!(),
         }
     }