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Add time measurement
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julian-hartl committed Mar 29, 2024
1 parent 83f3834 commit a142d52
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Showing 4 changed files with 34 additions and 10 deletions.
26 changes: 20 additions & 6 deletions ir/crates/back/src/codegen/register_allocator/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -134,11 +134,26 @@ impl Lifetime {
///
/// Keeps the ranges sorted by start point.
pub fn add_range(&mut self, range: LiveRange) {
let index = self
.ranges
.binary_search_by(|existing_range| existing_range.start.cmp(&range.start))
.unwrap_or_else(|index| index);
self.ranges.insert(index, range);
// todo: improve performance
let mut new_ranges = SmallVec::new();
let mut added = false;
for existing_range in &self.ranges {
if LiveRange::are_adjacent(existing_range, &range) {
let new_range = LiveRange {
start: std::cmp::min(existing_range.start, range.start),
end: std::cmp::max(existing_range.end, range.end),
};
new_ranges.push(new_range);
added = true;
} else {
new_ranges.push(existing_range.clone());
}
}
if !added {
new_ranges.push(range);
}
new_ranges.sort_by(|a: &LiveRange, b| a.start.cmp(&b.start));
self.ranges = new_ranges;
}

pub fn start(&self) -> ProgPoint {
Expand Down Expand Up @@ -695,7 +710,6 @@ impl<'liveness, 'func, TM: TargetMachine, RegAlloc: RegAllocAlgorithm<'liveness,
} else {
debug!("No register available for {vreg}. Retrying later");
worklist.push_back((vreg, instr_uid));
debug!("Worklist: {:?}", worklist);
}
}

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4 changes: 2 additions & 2 deletions ir/crates/back/src/codegen/targets/x86_64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -508,8 +508,8 @@ impl machine::isa::MachInstr for Instr {
Self::CMP32rr { lhs, rhs } => {
smallvec![InstrOperand::Reg(*lhs), InstrOperand::Reg(*rhs)]
}
Self::CMP32ri { lhs, .. } => smallvec![InstrOperand::Reg(*lhs),],
Self::CMP8ri { lhs, .. } => smallvec![InstrOperand::Reg(*lhs),],
Self::CMP32ri { lhs, rhs } => smallvec![InstrOperand::Reg(*lhs),InstrOperand::Imm(*rhs)],
Self::CMP8ri { lhs, rhs } => smallvec![InstrOperand::Reg(*lhs),InstrOperand::Imm(*rhs)],
Self::SETCC { dest, .. } => smallvec![InstrOperand::Reg(*dest)],
Self::JCC { target, .. } => smallvec![InstrOperand::Label(*target),],
}
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12 changes: 11 additions & 1 deletion ir/crates/compiler/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -27,29 +27,39 @@ fn valid_source_file_extension(file_path: &str) -> Result<PathBuf, String> {
Ok(file_path)
}

fn main() -> Result<()> {
fn main() -> Result<()> {
let start = std::time::Instant::now();
tracing_subscriber::fmt().with_max_level(tracing::Level::DEBUG).init();
let args = Args::parse();
let file_path = args.source_file;
let file_contents = std::fs::read_to_string(file_path)?;
let module = natrix_front::module::parse(&file_contents).map_err(
|e| anyhow::anyhow!("Failed to parse module: {}", e)
)?;
debug!("Took {:?} to parse module", start.elapsed());
let start = std::time::Instant::now();
println!("{:?}", module);
let mut module = FrontBridge::new().bridge(module);
println!("{:?}", module);
debug!("Took {:?} to bridge module", start.elapsed());
let start = std::time::Instant::now();
let mut config = optimization::PipelineConfig::o1();
config.dead_code_elimination = false;
// module.optimize(config);
debug!("Took {:?} to optimize module", start.elapsed());
let start = std::time::Instant::now();
println!("{module}");
let mut x86_mod = natrix_back::codegen::machine::module::Builder::<x86_64::Target>::new(&mut module).build();
x86_mod.run_register_allocator();
x86_mod.run_register_coalescer();
x86_mod.remove_fallthrough_jumps();
x86_mod.expand_pseudo_instructions();
debug!("Took {:?} to generate x86 module", start.elapsed());
let start = std::time::Instant::now();
debug!("{x86_mod}");
let base_addr = 0x1000;
let asm_module = x86_mod.assemble(base_addr);
debug!("Took {:?} to assemble x86 module", start.elapsed());
let mut emu = Emulator::new(
&asm_module
);
Expand Down
2 changes: 1 addition & 1 deletion ir/examples/arithmetic.nx
Original file line number Diff line number Diff line change
Expand Up @@ -10,5 +10,5 @@ bb2:
br bb1(v5, v6);
bb3:
v7 = add i32 v2, v2;
br bb1(v7, v3);
ret i32 v7;
}

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