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1. rv5_interface rv5_interface Public

   XC2C64A-5-VQ44 CPLD to interface with Boss RV-5

   VHDL 1

2. sorter sorter Public

   Verilog implementation of an AXIS number sorter

   Verilog

3. nasdaq_itch_pcap nasdaq_itch_pcap Public

   Experiments with ITCH PCAP files from NASDAQ's public FTP server

   Python

4. justinabate justinabate Public

   Profile formatting

5. Xilinx-ISE-Makefile Xilinx-ISE-Makefile Public

   Forked from WayneBooth/Xilinx-ISE-Makefile

   Xilinx ISE command line build flows (FPGA & CPLD)

   Makefile

6. ice_flow ice_flow Public

   Lattice iCEcube2 makefile build flow; targets iCEstick (iCE40-HX1K) and PWMs the LEDs

   Makefile