SystemVerilog Playground: Hacknight 6.0 Contribution

This repository showcases my contributions to the Hacknight 6.0 open-source hackathon.

Key Highlights

• SISO and SIPO Shift Registers: Implemented robust shift registers with serial input and serial or parallel output capabilities, catering to various communication needs.
• Prefix Adders: Developed efficient prefix adders using SystemVerilog for 4-, 8-, and 32-bit data, enabling high-performance arithmetic operations.
• Open-Source Contribution: Contributed to the SystemVerilog-Playground repository, fostering collaboration and knowledge sharing within the open-source hardware design community.

Functionality Breakdown

• Shift Registers:
  • siso_shift_register.sv: Implements a Serial Input, Serial Output (SISO) shift register for sequential data processing.
  • sipo_shift_register.sv: Offers a Serial Input, Parallel Output (SIPO) shift register for efficient data retrieval.
• Prefix Adders:
  • prefix_adder_4bit.sv: Delivers a 4-bit prefix adder for high-speed addition operations.
  • prefix_adder_8bit.sv: Provides an 8-bit prefix adder for broader data manipulation.
  • prefix_adder_32bit.sv: Caters to larger data sets with a 32-bit prefix adder architecture.

Hacknight 6.0 Contribution Details

• Awarded Bounty Points: Recognized with 80 bounty points for my contributions.
• Repository Link: Find the complete codebase on GitHub at https://github.com/acmpesuecc/SystemVerilog-Playground.

Acknowledgement

This project builds upon the foundation laid by Abhiram (https://github.com/alfadelta10010) through the creation of the SystemVerilog-Playground repository. Get Involved

Feel free to explore the code, experiment with the designs, and contribute your own ideas to further enhance this repository. The SystemVerilog community welcomes your participation!

License

This repository is distributed under the MIT License.

Additional Information

• For more information on SISO/SIPO shift registers and prefix adders, refer to these resources:
  • SISO Shift Registers: https://en.wikipedia.org/wiki/Shift_register
  • SIPO Shift Registers: https://en.wikipedia.org/wiki/Shift_register
  • Prefix Adders: https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Parallel%20prefix%20adders%20presentation.pdf