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add limitation note for SSC #3

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add limitation note for SSC #3

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88ae9f9
fix typo in README
Oct 30, 2019
beb7096
add limitation note for SSC
Oct 30, 2019
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19 changes: 11 additions & 8 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -77,14 +77,14 @@ Examples:
The naming convention is `<PCIeA><PCIeB><PCIeC><PCIeD>`. Where `<PCIeN>` is
one of the following protocols:

| Character | Description |
| --------- | ----------------- |
| `1` | PCIe x1 lane |
| `2` | PCIe x2 lane |
| `s` | SATA lane |
| `g` | SGMII lane |
| `q` | QSGMII lane |
| `_` | lane not avalable |
| Character | Description |
| --------- | ------------------ |
| `1` | PCIe x1 lane |
| `2` | PCIe x2 lane |
| `s` | SATA lane |
| `g` | SGMII lane |
| `q` | QSGMII lane |
| `_` | lane not available |

All variants only supports different SerDes protocols on SMARC PCIe A/B
lanes. Please note that the protocols in (brackets) are optional features
Expand All @@ -94,6 +94,9 @@ always have QSGMII on the PCIe D lane.
Due to a limitation of the LS1028A SoC, PCIe Gen3 cannot be used
simultaneously with SATA. Therefore, if a RCW with SATA is programmed, PCIe
will only negotiate to to PCIe Gen1 or Gen2.
If spread spectrum clock (SSC) is intended to use for PCIe,
the SGMII lanes will not work, because PCIe and SGMII use the same PLL and
SGMII can not work with SSC.

### Variant 2: Dual TSN port module

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