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kvsh2050/README.md
  • 👋 Hi, I’m @kvsh2050
  • 👀 I’m interested in Hardware, Security, Computer Architecture and Embedded systems !!!!!!!!
  • 🌱 I’m currently learning about RISC V and Bluespec and plan to implement in an FPGA
  • 💞️ I’m looking to collaborate on ANY RISC V or Hardware based projects!!
  • 📫 Reach me @ github
  • ⚡ Fun fact: I like coffee with milk ;)

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  1. verilog-ethernet verilog-ethernet Public

    Forked from alexforencich/verilog-ethernet

    Verilog Ethernet components for FPGA implementation

    VHDL 1