MEGA65 specific opcodes
This page tries to document the MEGA65 specific opcodes (which means any opcode over the opcode set of the Commodore 65). You can find detailed explanations on the meaning of the columns in this table, also many other important notes and warnings after the table, at the end of this page. Since all opcodes are used even on C65's CPU, the only way to add new opcodes on the MEGA65 is to interpret some opcode combinations as prefixes.
| opcode | syntax | Xemu status | c | A | D | comments |
|---|---|---|---|---|---|---|
424201 |
RESQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
424205 |
ORQ $nn |
OK | S | RQ | ||
424206 |
ASLQ $nn |
OK | S | MQ | ||
42420A |
ASLQ |
OK | - | Q | ||
42420D |
ORQ $nnnn |
OK | S | RQ | ||
42420E |
ASLQ $nnnn |
OK | S | MQ | ||
424211 |
RESQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
424212 |
ORQ ($nn) |
OK | S | RQ | ||
4242EA12 |
ORQ [$nn] |
OK | L | RQ | ||
EA12 |
ORA [$nn],Z |
OK | L | rb | ||
424215 |
RESQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424216 |
ASLQ $nn,X |
OK | S | MQ | ||
424219 |
RESQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
42421A |
INQ |
OK | - | Q | ||
42421D |
RESQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
42421E |
ASLQ $nnnn,X |
OK?? | S | MQ | ||
424221 |
RESQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
424224 |
BITQ $nn |
OK | S | RQ | ||
424225 |
ANDQ $nn |
OK | S | RQ | ||
424226 |
ROLQ $nn |
OK | S | MQ | ||
42422A |
ROLQ |
OK | - | Q | ||
42422C |
BITQ $nnnn |
OK | S | RQ | ||
42422D |
ANDQ $nnnn |
OK | S | RQ | ||
42422E |
ROLQ $nnnn |
OK | S | MQ | ||
424231 |
RESQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
424232 |
ANDQ ($nn) |
OK | S | RQ | ||
4242EA32 |
ANDQ [$nn] |
OK | L | RQ | ||
EA32 |
AND [$nn],Z |
OK | L | rb | ||
424234 |
RESQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424235 |
RESQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424236 |
ROLQ $nn,X |
OK | S | MQ | ||
424239 |
RESQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
42423A |
DEQ |
OK | - | Q | ||
42423C |
RESQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
42423D |
RESQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
42423E |
ROLQ $nnnn,X |
OK?? | S | MQ | ||
424241 |
RESQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
424243 |
ASRQ |
OK | - | Q | ||
424244 |
ASRQ $nn |
OK | S | MQ | ||
424245 |
EORQ $nn |
OK | S | RQ | ||
424246 |
LSRQ $nn |
OK | S | MQ | ||
42424A |
LSRQ |
OK | - | Q | ||
42424D |
EORQ $nnnn |
OK | S | RQ | ||
42424E |
LSRQ $nnnn |
OK | S | MQ | ||
424251 |
RESQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
424252 |
EORQ ($nn) |
OK | S | RQ | ||
4242EA52 |
EORQ [$nn] |
OK | L | RQ | ||
EA52 |
EOR [$nn],Z |
OK | L | rb | ||
424254 |
ASRQ $nn,X |
OK?? | S | MQ | ||
424255 |
RESQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424256 |
LSRQ $nn,X |
OK | S | MQ | ||
424259 |
RESQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
42425D |
RESQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
42425E |
LSRQ $nnnn,X |
OK | S | MQ | ||
424261 |
RESQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
424265 |
ADCQ $nn |
OK | S | RQ | ||
424266 |
RORQ $nn |
OK | S | MQ | ||
42426A |
RORQ |
OK | - | Q | ||
42426D |
ADCQ $nnnn |
OK | S | RQ | ||
42426E |
RORQ $nnnn |
OK | S | MQ | ||
424271 |
RESQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
424272 |
ADCQ ($nn) |
OK | S | RQ | ||
4242EA72 |
ADCQ [$nn] |
OK | L | RQ | ||
EA72 |
ADC [$nn],Z |
OK | L | rb | ||
424275 |
RESQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424276 |
RORQ $nn,X |
OK | S | MQ | ||
424279 |
RESQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
42427D |
RESQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
42427E |
RORQ $nnnn,X |
OK | S | MQ | ||
424281 |
RSVQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
424282 |
RSVQ ($nn,SP),Y |
MEGA65-RESERVED | - | - | - | - |
424285 |
STQ $nn |
OK | S | WQ | ||
42428D |
STQ $nnnn |
OK | S | WQ | ||
424291 |
RSVQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
424292 |
STQ ($nn) |
OK | S | WQ | ||
4242EA92 |
STQ [$nn] |
OK | L | WQ | ||
EA92 |
STA [$nn],Z |
OK | L | wb | ||
424295 |
RSVQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
424299 |
RSVQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
42429D |
RSVQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
4242A1 |
RSVQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
4242A5 |
LDQ $nn |
OK | S | RQ | ||
4242AD |
LDQ $nnnn |
OK | S | RQ | ||
4242B1 |
LDQ ($nn),Y |
?????? | S | RQ | ||
4242B2 |
LDQ ($nn),Z |
OK | S | RQ | ||
4242EAB2 |
LDQ [$nn],Z |
OK | L | RQ | ||
EAB2 |
LDA [$nn],Z |
OK | L | rb | ||
4242B5 |
LDQ $nn,X |
?????? | S | RQ | ||
4242B9 |
LDQ $nnnn,Y |
?????? | S | RQ | ||
4242BD |
LDQ $nnnn,X |
?????? | S | RQ | ||
4242C1 |
RSVQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
4242C5 |
CMPQ $nn |
OK | S | RQ | ||
4242C6 |
DEQ $nn |
OK | S | MQ | ||
4242CD |
CMPQ $nnnn |
OK | S | RQ | ||
4242CE |
DEQ $nnnn |
OK | S | MQ | ||
4242D1 |
RSVQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
4242D2 |
CMPQ ($nn) |
OK | S | RQ | ||
4242EAD2 |
CMPQ [$nn] |
OK | L | RQ | ||
EAD2 |
CMP [$nn],Z |
OK | L | rb | ||
4242D5 |
RSVQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
4242D6 |
DEQ $nn,X |
OK?? | S | MQ | ||
4242D9 |
RSVQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
4242DD |
RSVQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
4242DE |
DEQ $nnnn,X |
OK?? | S | MQ | ||
4242E1 |
RSVQ ($nn,X) |
MEGA65-RESERVED | - | - | - | - |
4242E2 |
LDQ ($nn,SP),Y |
?????? | S | RQ | ||
4242E5 |
SBCQ $nn |
OK | S | RQ | ||
4242E6 |
INQ $nn |
OK | S | MQ | ||
4242ED |
SBCQ $nnnn |
OK | S | RQ | ||
4242EE |
INQ $nnnn |
OK | S | MQ | ||
4242F1 |
RSVQ ($nn),Y |
MEGA65-RESERVED | - | - | - | - |
4242F2 |
SBCQ ($nn) |
OK | S | RQ | ||
4242EAF2 |
SBCQ [$nn] |
OK | L | RQ | ||
EAF2 |
SBC [$nn],Z |
OK | L | rb | ||
4242F5 |
RSVQ $nn,X |
MEGA65-RESERVED | - | - | - | - |
4242F6 |
INQ $nn,X |
OK | S | MQ | ||
4242F9 |
RSVQ $nnnn,Y |
MEGA65-RESERVED | - | - | - | - |
4242FD |
RSVQ $nnnn,X |
MEGA65-RESERVED | - | - | - | - |
4242FE |
INQ $nnnn,X |
OK | S | MQ |
-
opcode column: the full opcode with prefix(es). Assembler writers may want to be sure and warn the user, if the user accidentally creates these sequences, by other means than using the described syntax, which can cause surprising results for them.
-
syntax column: the recommended assembly syntax. Note, that things like "ASLQ" (if there is further argument!) may be understood as "ASL Q" as well, just like "ASL" alone can be "ASL A" and vice-versa in many assemblers.
-
Xemu status column:
-
MEGA65-RESERVED: reserved opcode even on MEGA65, not implemented in Xemu either, for sure -
MEGA65-ISSUE: the opcode has problems on MEGA65 or some uncertainity in its behaviour still, not implemented yet in Xemu, because of this -
OK: emulation is implemented in Xemu (in official builds), and - to my best knowledge - there is no issue with the emulated behaviour -
OK??: there is some emulation here, but it's unclear that this opcode should even exist/work on MEGA65 and not reserved (since uses X or Y indexing) -
WIP: emulation is work-in-progress and testing in "unofficial" Xemu branches, probably does not exist in stable/next Xemu branches/builds -
MAYBE: emulation is considered as complete, it's at least committed to the "dev" branch (so probably not in master and next branches though!) but issues can exist still -
TODO: there is no work yet on this opcode -
??????: not clear for me, that it should even work or not, at all (no emulation in Xemu)
-
-
"c" (cycles) column: number of CPU cycles (cycles needed for the prefix bytes to be executed are included)
-
"A" (address) column:
-
S: Short, standard 65xx-like 16-bit (short) addressing with various addressing modes, indicated by "syntax" field, the resulted 16 bit address is routed through the normal CPU address translation -
L: Long, MEGA65-specific 32-bit long (28 for real, as MEGA65's address space is 28 bit wide) base page (ZP) "pointer", with or without the "Z" register, the resulted 32 bit address is physical address and not routed through any address translation
-
-
"D" (data) column:
-
RQ: Read Quad, opcode reads 32-bit data quantity -
WQ: Write Quad, opcode writes 32-bit data quantity -
MQ: Modify Quad, opcode is a 32-bit RMW (read-modify-write) opcode, reading (then modifying, without affecting the Q-register) and writing back -
rb: Read Byte, opcode reads 8-bit data quantity -
wb: Write Byte, opcode writes 8 bit data quantity -
Q: Q-register, opcode does not operate on memory but only on the 32-bit "Q" register (AXYZ)
-
- "MEGA65 specific opcode" means anything over the Commodore 65 opcode set (which itself is a 65CE02 opcode set, just using the special MAP opcode instead of the reserved AUG and NOP has a side-effect if it's after a MAP), otherwise MEGA65 is backward compatible with C65 in this regard, except for:
- It's not totally clear if "undefined BCD behaviour" is NMOS or CMOS 65xx like, probably CMOS on a real C65, but for better C64 compatibility, it's NMOS in case of the MEGA65
- C65's CPU has a "bug fixed" RMW (read-modify-write) behaviour, which is a problem for many C64 "legacy" code, when RMW opcode (exploiting the actual "bug") is used to acknowledge interrupts. Because of this, MEGA65 implements the NMOS 65xx-like behaviour
- The recommended assembly syntax for MEGA65 opcodes sometimes uses four letters than the usual three. Indeed, it's not so "nice" but otherwise it would be very hard to have easy to remember and meaningfull names. For example ASRQ and ASLQ can be both ASQ, how to make difference in three letters to avoid any confusion then what this opcode does.
- Information on this page has been collected by me (LGB) from various resources and also from personal experience. I cannot say, everything 100% correct here. Also on the MEGA65 side, there can be still changes going on!
- RESQ and RSVQ opcodes are seems to be reserved for future use, and their current behaviour is not defined at all (probably it will be executed as an opcode like without any MEGA65 specific prefix)
- these opcodes can be used only if enabled by hypervisor ($D67D.1)
-
these opcodes are unsafe to be used at 1MHz or 2MHz speeds, since atomic execution of prefix+opcodes are not guaranteed at 6502-timing mode!(this has already been fixed in MEGA65 implementation also in Xemu) - It seems for ADCQ/SBCQ, the "D" (decimal flag) is ignored for "Q" data mode, or at least it's a "not defined behaviour". Also it seems there is some oddity with the carry flag (not so clear yet) that carry is set if the unsigned result is greater than $FF, so it's not a real carry in 32-bit sense as "should be" logically?? Probably the opposite on carry flag happens with SBCQ ("borrow"), as with SBC vs ADC on 65xx CPUs.
- Do not confuse 32 bit addressing (NOP in the prefix, [...] or [...],Z) with 32 bit data (NEG-NEG in prefix, "Q" in name) notions! Though there are some opcodes both can be applied for the same time, though it seems order is important, in this case, only NEG-NEG-NOP is accepted, not the opposite.
- Q-register is a 32 bit register, though it consits of AXYZ, thus modifying any of the four 8 bit CPU registers has effect on Q, and vice-versa
- 32 bit addressing uses the "Z" index register, if data is 8 bit (Q opcode). However in case if it's both of 32-bit data (that is, it's a Q-opcode) and 32-bit addressing, this makes no sense, as Z is part of Q, when it's ignored. UNLESS, if the opcode is RMW (read-modify-write) or LDQ, when it's not a limitation, thus Z is included. (FIXME?)
