targets: Use full imports (vendor_board).

litex_boards/targets/aliexpress_stlv7325.py

@@ -13,7 +13,7 @@
 
 from migen import *
 
-from litex_boards.platforms import stlv7325
+from litex_boards.platforms import aliexpress_stlv7325
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -64,7 +64,7 @@ def __init__(self, sys_clk_freq=int(100e6),
         with_pcie       = False,
         with_sata       = False,
         **kwargs):
-        platform = stlv7325.Platform()
+        platform = aliexpress_stlv7325.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/aliexpress_xc7k420t.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import xc7k420t
+from litex_boards.platforms import aliexpress_xc7k420t
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
@@ -38,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs):
-        platform = xc7k420t.Platform()
+        platform = aliexpress_xc7k420t.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/alinx_ax7010.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import ax7010
+from litex_boards.platforms import alinx_ax7010
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.interconnect import axi
@@ -36,7 +36,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
-        platform = ax7010.Platform()
+        platform = alinx_ax7010.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -11,7 +11,7 @@
 
 from migen import *
 
-from litex_boards.platforms import datacenter_ddr4_test_board
+from litex_boards.platforms import antmicro_datacenter_ddr4_test_board
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -77,7 +77,7 @@ def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_reset_time="10e-3", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_spi_flash=False,
             with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
-        platform = datacenter_ddr4_test_board.Platform()
+        platform = antmicro_datacenter_ddr4_test_board.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         with_video_pll = (with_video_terminal or with_video_framebuffer)

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -7,7 +7,7 @@
 
 from migen import *
 
-from litex_boards.platforms import lpddr4_test_board
+from litex_boards.platforms import antmicro_lpddr4_test_board
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -49,7 +49,7 @@ def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
             with_led_chaser=True, **kwargs):
-        platform = lpddr4_test_board.Platform()
+        platform = antmicro_lpddr4_test_board.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)

litex_boards/targets/decklink_intensity_pro_4k.py

@@ -12,7 +12,7 @@
 
 from migen import *
 
-from litex_boards.platforms import intensity_pro_4k
+from litex_boards.platforms import decklink_intensity_pro_4k
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -41,7 +41,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
-        platform = intensity_pro_4k.Platform()
+        platform = decklink_intensity_pro_4k.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/decklink_mini_4k.py

@@ -14,7 +14,7 @@
 
 from migen import *
 
-from litex_boards.platforms import mini_4k
+from litex_boards.platforms import decklink_mini_4k
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -74,7 +74,7 @@ class BaseSoC(SoCMini):
     def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         if with_video_terminal or with_video_framebuffer:
             sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk.
-        platform = mini_4k.Platform()
+        platform = decklink_mini_4k.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -17,7 +17,7 @@
 
 from migen import *
 
-from litex_boards.platforms import quad_hdmi_recorder
+from litex_boards.platforms import decklink_quad_hdmi_recorder
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -59,7 +59,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs):
-        platform = quad_hdmi_recorder.Platform()
+        platform = decklink_quad_hdmi_recorder.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/digilent_arty.py

@@ -13,7 +13,7 @@
 
 from migen import *
 
-from litex_boards.platforms import arty
+from litex_boards.platforms import digilent_arty
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -71,7 +71,7 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
                  eth_dynamic_ip=False, with_led_chaser=True, with_jtagbone=True,
                  with_spi_flash=False, with_pmod_gpio=False, **kwargs):
-        platform = arty.Platform(variant=variant, toolchain=toolchain)
+        platform = digilent_arty.Platform(variant=variant, toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
         with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
@@ -120,7 +120,7 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
 
         # GPIOs ------------------------------------------------------------------------------------
         if with_pmod_gpio:
-            platform.add_extension(arty.raw_pmod_io("pmoda"))
+            platform.add_extension(digilent_arty.raw_pmod_io("pmoda"))
             self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
 
 # Build --------------------------------------------------------------------------------------------
@@ -168,9 +168,9 @@ def main():
         **soc_core_argdict(args)
     )
     if args.sdcard_adapter == "numato":
-        soc.platform.add_extension(arty._numato_sdcard_pmod_io)
+        soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io)
     else:
-        soc.platform.add_extension(arty._sdcard_pmod_io)
+        soc.platform.add_extension(digilent_arty._sdcard_pmod_io)
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
     if args.with_sdcard:

litex_boards/targets/digilent_arty_s7.py

@@ -9,7 +9,7 @@
 
 from migen import *
 
-from litex_boards.platforms import arty_s7
+from litex_boards.platforms import digilent_arty_s7
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -49,7 +49,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
-        platform = arty_s7.Platform(variant=variant)
+        platform = digilent_arty_s7.Platform(variant=variant)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/digilent_atlys.py

@@ -15,7 +15,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import atlys
+from litex_boards.platforms import digilent_atlys
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
@@ -149,7 +149,7 @@ def __init__(self, platform, sys_clk_freq):
 class BaseSoC(SoCCore):
     def __init__(self, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs):
         sys_clk_freq = int(75e6)
-        platform     = atlys.Platform()
+        platform     = digilent_atlys.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/digilent_basys3.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import basys3
+from litex_boards.platforms import digilent_basys3
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import SoCRegion
@@ -38,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
-        platform = basys3.Platform()
+        platform = digilent_basys3.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -81,7 +81,7 @@ def main():
         with_video_terminal    = args.with_video_terminal,
         **soc_core_argdict(args)
     )
-    soc.platform.add_extension(basys3._sdcard_pmod_io)
+    soc.platform.add_extension(digilent_basys3._sdcard_pmod_io)
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
     if args.with_sdcard:

litex_boards/targets/digilent_genesys2.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import genesys2
+from litex_boards.platforms import digilent_genesys2
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -46,7 +46,7 @@ def __init__(self, platform, sys_clk_freq):
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
                  with_led_chaser=True, **kwargs):
-        platform = genesys2.Platform()
+        platform = digilent_genesys2.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/digilent_nexys4ddr.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import nexys4ddr
+from litex_boards.platforms import digilent_nexys4ddr
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import SoCRegion
@@ -54,7 +54,7 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  **kwargs):
-        platform = nexys4ddr.Platform()
+        platform = digilent_nexys4ddr.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/digilent_nexys_video.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import nexys_video
+from litex_boards.platforms import digilent_nexys_video
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
@@ -77,7 +77,7 @@ class BaseSoC(SoCCore):
     def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False,
                  with_led_chaser=True, with_sata=False, sata_gen="gen2", with_sata_pll_refclk=False, vadj="1.2V", with_video_terminal=False,
                  with_video_framebuffer=False, **kwargs):
-        platform = nexys_video.Platform(toolchain=toolchain)
+        platform = digilent_nexys_video.Platform(toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
         with_video_pll = (with_video_terminal or with_video_framebuffer)

litex_boards/targets/digilent_pynq_z1.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import pynq_z1
+from litex_boards.platforms import digilent_pynq_z1
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.interconnect import axi
@@ -59,7 +59,7 @@ def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_vi
 class BaseSoC(SoCCore):
     def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True,
                 with_video_terminal=False, with_video_framebuffer=False, **kwargs):
-        platform = pynq_z1.Platform()
+        platform = digilent_pynq_z1.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal)

litex_boards/targets/enclustra_mercury_kx2.py

@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import mercury_kx2
+from litex_boards.platforms import enclustra_mercury_kx2
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -44,7 +44,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
-        platform = mercury_kx2.Platform()
+        platform = enclustra_mercury_kx2.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/enclustra_mercury_xu5.py

@@ -9,7 +9,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import mercury_xu5
+from litex_boards.platforms import enclustra_mercury_xu5
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
@@ -52,7 +52,7 @@ def __init__(self, platform, sys_clk_freq):
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
-        platform = mercury_xu5.Platform()
+        platform = enclustra_mercury_xu5.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/gsd_butterstick.py

@@ -15,7 +15,7 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import butterstick
+from litex_boards.platforms import gsd_butterstick
 
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
@@ -87,7 +87,7 @@ def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_
         with_led_chaser  = True,
         with_syzygy_gpio = True,
         **kwargs)       :
-        platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
+        platform = gsd_butterstick.Platform(revision=revision, device=device ,toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -145,7 +145,7 @@ def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_
 
         # GPIOs ------------------------------------------------------------------------------------
         if with_syzygy_gpio:
-            platform.add_extension(butterstick.raw_syzygy_io("SYZYGY0"))
+            platform.add_extension(gsd_butterstick.raw_syzygy_io("SYZYGY0"))
             self.submodules.gpio = GPIOTristate(platform.request("SYZYGY0"))
 
 # Build --------------------------------------------------------------------------------------------

litex_boards/targets/gsd_orangecrab.py

@@ -13,7 +13,7 @@
 from migen.genlib.misc import WaitTimer
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import orangecrab
+from litex_boards.platforms import gsd_orangecrab
 
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
@@ -146,7 +146,7 @@ def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
 class BaseSoC(SoCCore):
     def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
                  sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs):
-        platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
+        platform = gsd_orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------
         crg_cls      = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG