add litei2c

.github/workflows/ci.yml

@@ -47,50 +47,55 @@ jobs:
             ./overlay.config
 
   Zephyr-build:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     needs: Bitstream-build
     steps:
-      - uses: actions/checkout@v4
-
       - uses: actions/download-artifact@v4
         with:
           name: Bitstream-build
 
       - name: Install dependencies
         run: |
           sudo apt update
-          sudo apt-get install -y --no-install-recommends ninja-build gperf ccache dfu-util device-tree-compiler libssl-dev gcc g++ python3-dev python3-pip
-          sudo apt update
-          sudo apt-get install -y --no-install-recommends python3-setuptools python3-tk python3-wheel xz-utils file  make gcc gcc-multilib g++-multilib libmagic1 libsdl2-dev
+          sudo apt-get install -y --no-install-recommends git cmake ninja-build gperf \
+            ccache dfu-util device-tree-compiler wget \
+            python3-dev python3-pip python3-setuptools python3-tk python3-wheel xz-utils file \
+            make gcc gcc-multilib g++-multilib libsdl2-dev libmagic1 python3-venv
 
-      - name: Download Zephyr SDK
+      - name: Create Python virtual environment
         run: |
-          wget -q -O - https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.8/zephyr-sdk-0.16.8_linux-x86_64.tar.xz | tar -J -xf -
+          python3 -m venv .venv
+          source .venv/bin/activate
+          echo "VIRTUAL_ENV=${VIRTUAL_ENV}" >> $GITHUB_ENV
+          echo "${VIRTUAL_ENV}/bin" >> $GITHUB_PATH
+        shell: bash
 
       - name: Prepare Zephyr
         run: |
-          pip3 install west
+          pip install west
           west init zephyrproject
           cd zephyrproject/
+          west config manifest.group-filter -- -hal,-tools,-bootloader,-babblesim
+          west config manifest.project-filter -- -nrf_hw_models
+          west config --global update.narrow true
           west update
           west zephyr-export
-          pip3 install -r zephyr/scripts/requirements.txt
+          west packages pip --install
           cd ..
 
       - name: Install Zephyr SDK
         run: |
-          cd zephyr-sdk-*
-          ./setup.sh -h -t riscv64-zephyr-elf
-          cd ../
+          cd zephyrproject/zephyr
+          west sdk install -H -t riscv64-zephyr-elf
+          cd ../../
 
       - name: Build Zephyr App
         run: |
-          export ZEPHYR_SDK_INSTALL_DIR=$PWD
           cd zephyrproject/zephyr
           cat ../../Bitstream-build/overlay.config | xargs west build -b litex_vexriscv samples/philosophers/ -- -DDTC_OVERLAY_FILE= ../../Bitstream-build/overlay.dts
           cd ../../
 
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         with:
           name: ${{github.job}}
           path: ./zephyrproject/zephyr/build/zephyr/zephyr.bin

.gitmodules

@@ -49,3 +49,6 @@
 [submodule "third_party/pythondata-software-picolibc"]
 	path = third_party/pythondata-software-picolibc
 	url = https://github.com/litex-hub/pythondata-software-picolibc.git
+[submodule "third_party/litei2c"]
+	path = third_party/litei2c
+	url = https://github.com/litex-hub/litei2c

init

@@ -1,7 +1,7 @@
 export PATH="${PWD}/third_party/litex/litex/tools:$PATH"
 export PATH="${PWD}/tools/conda/bin:$PATH"
 
-directories=(litedram liteeth liteiclink litepcie litespi litesata litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)
+directories=(litedram liteeth litei2c liteiclink litepcie litespi litesata litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)
 
 for directory in "${directories[@]}";
 do

make.py

@@ -78,6 +78,7 @@ def main():
     parser.add_argument("--with_spi", action="store_true", help="Enable spi (Arty target only)")
     parser.add_argument("--with_spi_flash", action="store_true", help="Enable spi flash (Arty target only)")
     parser.add_argument("--with_i2c", action="store_true", help="Enable i2c (Arty target only)")
+    parser.add_argument("--with_litei2c", action="store_true", help="Enable i2c via litei2c (Arty target only)")
     parser.add_argument("--with_pwm", action="store_true", help="Enable pwm (Arty target only)")
     parser.add_argument("--spi-data-width", type=int, default=8,      help="SPI data width (maximum transfered bits per xfer, Arty target only)")
     parser.add_argument("--spi-clk-freq",   type=int, default=1e6,    help="SPI clock frequency (Arty target only)")
@@ -154,6 +155,8 @@ def main():
                 soc.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate=args.spi_flash_rate, with_master=True)
             if args.with_i2c:
                 soc.add_i2c()
+            if args.with_litei2c:
+                soc.add_litei2c()
             if args.with_i2s:
                 if not args.with_mmcm:
                     print("Adding mmcm implicitly, cause i2s core needs special clk signals")

soc_zephyr.py

@@ -16,6 +16,8 @@
 
 from liteeth.phy.mii import LiteEthPHYMII
 
+from litei2c import LiteI2C
+
 # Helpers ------------------------------------------------------------------------------------------
 
 def platform_request_all(platform, name):
@@ -52,6 +54,7 @@ class _SoCZephyr(soc_cls):
             "spiflash_core":   24, # addr: 0xe000c000
             "spiflash_phy":    25, # addr: 0xe000c800
             "watchdog0":  26, # addr: 0xe000d000
+            "litei2c":    27, # addr: 0xe000d800
         }}
 
         interrupt_map = {**soc_cls.interrupt_map, **{
@@ -90,6 +93,12 @@ def add_rgb_led(self):
 
         def add_i2c(self):
             self.submodules.i2c0 = I2CMaster(self.platform.request("i2c", 0))
+
+        def add_litei2c(self):
+            self.litei2c = LiteI2C(
+                sys_clk_freq=self.sys_clk_freq,
+                pads=self.platform.request("i2c", 0)
+            )
 
         def add_i2s(self):
             self.platform.add_extension(arty_platform._i2s_pmod_io)