[WIP] fofb_shaper_filt: add module

hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh

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+#!/bin/bash
+
+mkdir -p doc
+cheby -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd

hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby

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+memory-map:
+  bus: wb-32-be
+  name: wb_iir_filt_regs
+  description: Interface to FOFB IIR shaper filters regs
+  x-hdl:
+    busgroup: True
+    iogroup: wb_iir_filt_regs_ifc
+  children:
+    - repeat:
+        name: ch
+        count: 12
+        children:
+          - memory:
+              name: coeffs
+              memsize: 200
+              description: |
+                Coefficients for the ceil('max_filt_order'/2) IIR internal
+                biquads.
+
+                Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1).
+                The 'coeffs' array should be populated in the following manner:
+
+                  coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx}
+                  coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx}
+                  coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx}
+                  coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
+                  coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}
+
+                This array acts like a 'shadow' for the real coefficients and is
+                only effectived when '1' is written to 'eff_coeffs' bit of 'ctl'
+                register.
+
+                NOTE: This ABI supports up to 20th order filters, but only the
+                coefficients corresponding to the first 'max_filt_order' filters
+                are meaningful for the gateware.
+              children:
+                - reg:
+                    name: val
+                    width: 32
+                    access: rw
+                    description: |
+                      Coefficient value using 'coeffs_fp_repr' fixed-point
+                      representation. It should be aligned to the left.
+    - reg:
+        name: max_filt_order
+        width: 32
+        access: ro
+        description: |
+          Maximum filter order supported by the gateware.
+    - reg:
+        name: coeffs_fp_repr
+        width: 32
+        access: ro
+        description: |
+          Fixed-point representation of coefficients.
+        children:
+          - field:
+              name: int_width
+              range: 4-0
+              description: |
+                Integer width.
+          - field:
+              name: frac_width
+              range: 9-5
+              description: |
+                Fractionary width.
+    - reg:
+        name: ctl 
+        width: 32
+        access: rw
+        description: |
+          Control register.
+        children:
+          - field:
+              name: eff_coeffs
+              x-hdl:
+                type: autoclear
+              range: 0
+              description: |
+                Strobe for effectivating (i.e. updating) coefficients.
+              comment: |
+                write 0: no effect
+                write 1: effectivates coefficients (this bit autoclears)

hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h

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+#ifndef __CHEBY__WB_IIR_FILT_REGS__H__
+#define __CHEBY__WB_IIR_FILT_REGS__H__
+#define WB_IIR_FILT_REGS_SIZE 4108 /* 0x100c */
+
+/* None */
+#define WB_IIR_FILT_REGS_CH 0x0UL
+#define WB_IIR_FILT_REGS_CH_SIZE 256 /* 0x100 */
+
+/* Coefficients for the ceil('max_filt_order'/2) IIR internal
+biquads.
+
+Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1).
+The 'coeffs' array should be populated in the following manner:
+
+  coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx}
+  coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx}
+  coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx}
+  coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
+  coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}
+
+This array acts like a 'shadow' for the real coefficients and is
+only effectived when '1' is written to 'eff_coeffs' bit of 'ctl'
+register.
+
+NOTE: This ABI supports up to 20th order filters, but only the
+coefficients corresponding to the first 'max_filt_order' filters
+are meaningful for the gateware.
+ */
+#define WB_IIR_FILT_REGS_CH_COEFFS 0x0UL
+#define WB_IIR_FILT_REGS_CH_COEFFS_SIZE 4 /* 0x4 */
+
+/* Coefficient value using 'coeffs_fp_repr' fixed-point
+representation. It should be aligned to the left.
+ */
+#define WB_IIR_FILT_REGS_CH_COEFFS_VAL 0x0UL
+
+/* Maximum filter order supported by the gateware.
+ */
+#define WB_IIR_FILT_REGS_MAX_FILT_ORDER 0x1000UL
+
+/* Fixed-point representation of coefficients.
+ */
+#define WB_IIR_FILT_REGS_COEFFS_FP_REPR 0x1004UL
+#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_MASK 0x1fUL
+#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_SHIFT 0
+#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL
+#define WB_IIR_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_SHIFT 5
+
+/* Control register.
+ */
+#define WB_IIR_FILT_REGS_CTL 0x1008UL
+#define WB_IIR_FILT_REGS_CTL_EFF_COEFFS 0x1UL
+
+struct wb_iir_filt_regs {
+  /* [0x0]: REPEAT (no description) */
+  struct ch {
+    /* [0x0]: MEMORY Coefficients for the ceil('max_filt_order'/2) IIR internal
+biquads.
+
+Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1).
+The 'coeffs' array should be populated in the following manner:
+
+  coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx}
+  coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx}
+  coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx}
+  coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx}
+  coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx}
+
+This array acts like a 'shadow' for the real coefficients and is
+only effectived when '1' is written to 'eff_coeffs' bit of 'ctl'
+register.
+
+NOTE: This ABI supports up to 20th order filters, but only the
+coefficients corresponding to the first 'max_filt_order' filters
+are meaningful for the gateware.
+ */
+    struct coeffs {
+      /* [0x0]: REG (rw) Coefficient value using 'coeffs_fp_repr' fixed-point
+representation. It should be aligned to the left.
+ */
+      uint32_t val;
+    } coeffs[50];
+  } ch[12];
+
+  /* [0x1000]: REG (ro) Maximum filter order supported by the gateware.
+ */
+  uint32_t max_filt_order;
+
+  /* [0x1004]: REG (ro) Fixed-point representation of coefficients.
+ */
+  uint32_t coeffs_fp_repr;
+
+  /* [0x1008]: REG (rw) Control register.
+ */
+  uint32_t ctl;
+};
+
+#endif /* __CHEBY__WB_IIR_FILT_REGS__H__ */