[capture] Add delay to AES FPGA capture #391
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Unfortunately, the UART connection to the FPGA is quite iffy. It turns out that a small delay for the FvsrKeyBatchEncrypt cmd is needed. Otherwise, the command sometimes gets not received by the device. This happens with the latest CW310 firmware as well as UART control flow enabled in the SW. This was detected now as on silicon this problem does not occur. Signed-off-by: Pascal Nasahl <[email protected]>
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Unfortunately, the UART connection to the FPGA is quite iffy. It turns out that a small delay for the FvsrKeyBatchEncrypt cmd is needed. Otherwise, the command sometimes gets not received by the device. This happens with the latest CW310 firmware as well as UART control flow enabled in the SW.
This was detected now as on silicon this problem does not occur.