spiflash: A proposed SPI controller for reading

[ghost]

On this pull request, I propose an SPI flash controller module exclusively for reading data or registers out of a flash device. Currently, it has:

• _SPIFlashReaderBase: a base class from which can be inherited to create a new controller module, such as one that reads the ID of the flash device by issuing the opcode 0x9F (or 0x9E)
• SPIFlashSlowReader: a module for normal reads from the device, meaning no dummy cycles of waiting is needed right after sending the address bytes to the device, while the read frequency is often capped.
• SPIFlashFastReader: a module for "fast reads", meaning a faster frequency than normal reads while a number of dummy cycles of waiting is needed right after sending the address bytes.

Note that only the SlowReader but not the FastReader has been successfully tested on the ECP5 evaluation board.

In order to use the clock signal clk as the SPI clock for this module design, ECP5 requires the user NOT to request for SPI clock that corresponds to the on-chip oscillator (MCLK) but to instantiate a USRMCLK Instance. Therefore, to use this module and bulid the configuration bitstream on nextpnr without errors (see this comment), the user must avoid requesting for the normal clock pin from Ball U3 by some means. One way is to use my proposed modification of nmigen-boards.

I look forward to seeing further comments, thanks.

[sbourdeauducq]

I don't think this should be part of this PR. Is there a special feature from nmigen 0.1rc1 that this PR requires?
In any case I don't think it makes sense to track releases yet, since everything is still in flux.

[ghost]

So far the only issue with 0.1RC1 I have encountered is that what was called nmigen.tools is now nmigen.utils, and RC1 doesn't seem to give any backward compatibility. Since Minerva has already been updated to RC1, for the purpose of HeavyX nmigen-stdio does require 0.1RC1 in order to bulid the bitstream.

I also noticed nmigen-soc is using 0.1RC1. @whitequark may I know why 0.1RC1 is used there?

[whitequark]

Probably an oversight. Both nmigen-stdio and nmigen-soc should require nmigen~=X where X is the latest stable version, currently 0.1.

[sbourdeauducq]

There may be an option to look at the VCD manually, but the test should be ideally self-checking.

[ghost]

I factored out the USRMCLK primitive and fixed most of the styling on f87fa5e.

Currently test_spiflash.py only asserts whether the data read by the SPI readers match the memory content of a simulated SPI flash device; looking at the VCD is not necessary.

I haven't changed the nMigen version number lest it hasn't been finalised.

[mithro]

@HarryHo90sHK you might find some of the code I started working on at https://github.com/mithro/litex/tree/d7184b97494012a8c21ee93df231b758a61e9dec/litex/soc/cores/spi useful. It was suppose to create a spiflash module system like the DRAM module system in LiteDRAM.

[ghost]

6a1a23c fixed a typo only. Thank you @mithro for the comment and I think it is possible to adopt better encapsulation on the SPI logic. Essentially, an SPI master performs the following sequence in all types of READ commands:

Type	Duration	Direction
Command	equivalent of sending 8 bits	Master → Slave
Address	equivalent of sending 24 bits	Master → Slave
Dummy Cycles	≥0 cycles	--
Data	equivalent of sending ≥1 byte	Slave → Master

Adding support for all CPOL/CPHA pairs might be useful, though the N25Q128A chip I have been testing with only uses (0,0) and (1,1), not (0,1) or (1,0).