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feat(prover): parallelized memory queues simulation in BWG (#2652)
## What ❔ The updated logic of memory queue simulation in the test_harness requires changing the structure of the BWG artifacts. When processing memory queues for ram permutation circuit, part of the witness is sent to storage separately. For this reason, a new type of circuit wrapper has been added - partial base circuit. Also added logic required to transform a partial base layer circuit into a full one (merging structures) for WVG and proving. These changes can significantly reduce peak RAM usage in BWG, while speeding up the slowest part of the witness generation process. ## Checklist <!-- Check your PR fulfills the following items. --> <!-- For draft PRs check the boxes as you complete them. --> - [ ] PR title corresponds to the body of PR (we generate changelog entries from PRs). - [ ] Tests for the changes have been added / updated. - [ ] Documentation comments have been added / updated. - [ ] Code has been formatted via `zk fmt` and `zk lint`.
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