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rasdaemon: mce-amd-smca: Optimizing decoding of MCA_CTL_SMU bits #167

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rasdaemon: mce-amd-smca: Optimizing decoding of MCA_CTL_SMU bits #167

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29 changes: 3 additions & 26 deletions mce-amd-smca.c
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Original file line number Diff line number Diff line change
Expand Up @@ -421,7 +421,7 @@ static const char * const smca_smu_mce_desc[] = {
"An ECC or parity error in an SMU RAM instance",
};

static const char * smca_smu2_mce_desc[64] = {
static const char * const smca_smu2_mce_desc[] = {
"High SRAM ECC or parity error",
"Low SRAM ECC or parity error",
"Data Cache Bank A ECC or parity error",
Expand All @@ -434,14 +434,13 @@ static const char * smca_smu2_mce_desc[64] = {
"Instruction Tag Cache Bank B ECC or parity error",
"System Hub Read Buffer ECC or parity error",
"PHY RAS ECC Error",
};

static const char * smca_smu2_ext_mce_desc[] = {
[12 ... 57] = "Reserved",
"A correctable error from a GFX Sub-IP",
"A fatal error from a GFX Sub-IP",
"Reserved",
"Reserved",
"A poison error from a GFX Sub-IP",
"Reserved",
};

static const char * const smca_mp5_mce_desc[] = {
Expand Down Expand Up @@ -850,27 +849,6 @@ static struct smca_bank_name smca_names[] = {
[SMCA_GMI_PHY] = { "Global Memory Interconnect PHY Unit" },
};

void smca_smu2_ext_err_desc(void)
{
int i, j;
int smu2_bits = 62;

/*
* MCA_CTL_SMU error stings are defined for b'58:59 and b'62
* in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU
*
* b'0:11 can be decoded from existing array smca_smu2_mce_desc.
* b'12:57 are Reserved and b'58:62 are appended to the
* smca_smu2_mce_desc.
*/
for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) {
for ( ; i < 58; i++)
smca_smu2_mce_desc[i] = "Reserved";

smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j];
}
}

void amd_decode_errcode(struct mce_event *e)
{
decode_amd_errcode(e);
Expand Down Expand Up @@ -961,7 +939,6 @@ void decode_smca_error(struct mce_event *e, struct mce_priv *m)
mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID,
(ipid_high & MCI_IPID_MCATYPE) >> 16);

smca_smu2_ext_err_desc();
fixup_hwid(m, &mcatype_hwid);

for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
Expand Down
1 change: 0 additions & 1 deletion ras-mce-handler.h
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Expand Up @@ -127,7 +127,6 @@ int set_intel_imc_log(enum cputype cputype, unsigned ncpus);
/* Undertake AMD SMCA Error Decoding */
void decode_smca_error(struct mce_event *e, struct mce_priv *m);
void amd_decode_errcode(struct mce_event *e);
void smca_smu2_ext_err_desc(void);

/* Per-CPU-type decoders for Intel CPUs */
void p4_decode_model(struct mce_event *e);
Expand Down
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