Example Microsemi

It is possible to use vendor neutral verilog for initial testing - compliance tests are pretty small they would fit into LUT ROM. For Dhrystone or Zephyr some RAM init or XiP solution must be chosen. When using UART Bootloader or XiP from SPI Flash all code can remain vendor neutral. All other options involve the use of the hard IP Blocks in SmartFusion2/IGLOO2.

Take the exact same code as in Lattice Example Create Libero Project and add the verilog files, then create default testbench, and click simulate, open memory view and preload your RISCV code, add LED to wave and run simulation.

And you see how picorv32 is passing I-ADD-01 compliance test.

Step by step:

• Get the project: picorv32 project for Libero
• Open it in Libero
• Click Simulate (Modelsim opens)
• Click on system_0 in "sim" tab
• Drag DEBUG_LED from Objects to Wave
• Change sim time from 100fs to 100us, click on run icon
• Click on zoom Full

If you look in the memory view, you see the RV32I compliance test signature between BBBB ... EEEE

Please note that this design would FAIL on real FPGA as the inferred RAM would not hold the initialized constants for the test, Modelsim loaded them your FPGA would not.

You can look at the registers and RAM content using SmartDebug

Here is the mcycle counter as example. For memories you will only see the primitives, so it is hard to figure out that RAM bits are where.

Now it is time to decide what boot option you choose for your final design, the options are listed in SoC Design Section.