Hi, this is my fork of Assise, done as a semester project in CS380D at UT Austin. Here is my paper draft: https://drive.google.com/file/d/1XN1d-SiOR8WdauyVza9maBB9r3GoQLLW/view?usp=sharing describing it.

We disaggregate Assise's warm replicas into a distributed, disaggregated victim cache to improve resource utilization and cache hit rates. We also redesign the I/O path for reads, removing CPU intervention (and concurrency bottlenecks) and achieving single-round-trip, 1-sided RDMA reads, reducing read latency by 20%+. To achieve this, we use a combination of clock syncs and self-verifying data structures for writes. Utilizing NIC capabilities and multi-threading, we also speed up write throughput, reducing kernel digestion overhead, by around 5x.