iio: adc: ad9361: Export pl_intf_clk reflecing interface PL clock rate

This commit adds a new clock to the clock tree that reflects the actual
receive clock rate. For 1RX1TX configurations this simply mirrors the
sample clock, while for 2RX2TX configs the receive clock is twice as
fast as the sample clock, because two channels are served using the same
data width.

Signed-off-by: David Winter <[email protected]>

drivers/iio/adc/ad9361.c

@@ -5757,7 +5757,10 @@ static inline int ad9361_set_muldiv(struct refclk_scale *priv, u32 mul, u32 div)
 static int ad9361_get_clk_scaler(struct clk_hw *hw)
 {
 	struct refclk_scale *clk_priv = to_clk_priv(hw);
+	struct ad9361_rf_phy *phy = clk_priv->phy;
+	struct ad9361_phy_platform_data *pd = phy->pdata;
 	struct spi_device *spi = clk_priv->spi;
+	const bool lvds_mode = pd->port_ctrl.pp_conf[2] & LVDS_MODE;
 	u32 tmp, tmp1;
 
 	switch (clk_priv->source) {
@@ -5822,6 +5825,8 @@ static int ad9361_get_clk_scaler(struct clk_hw *hw)
 			tmp = (1 << (tmp - 1));
 
 		return ad9361_set_muldiv(clk_priv, 1, tmp);
+	case PL_INTF_CLK:
+		return ad9361_set_muldiv(clk_priv, (ad9361_uses_rx2tx2(phy) + 1) << lvds_mode, 1);
 	default:
 		return -EINVAL;
 	}
@@ -5990,6 +5995,8 @@ static int ad9361_set_clk_scaler(struct clk_hw *hw, bool set)
 			return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL,
 					TX_FIR_ENABLE_INTERPOLATION(~0), tmp);
 		break;
+	case PL_INTF_CLK:
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -6066,6 +6073,11 @@ static const struct clk_ops refclk_scale_ops = {
 	.recalc_rate = ad9361_clk_factor_recalc_rate,
 };
 
+static const struct clk_ops pl_intf_clk_ops = {
+	.round_rate = ad9361_clk_factor_round_rate,
+	.recalc_rate = ad9361_clk_factor_recalc_rate,
+};
+
 /*
  * BBPLL
  */
@@ -6587,6 +6599,9 @@ static int ad9361_clk_register(struct ad9361_rf_phy *phy,
 	case TX_RFPLL:
 		init.ops = &rfpll_clk_ops;
 		break;
+	case PL_INTF_CLK:
+		init.ops = &pl_intf_clk_ops;
+		break;
 	default:
 		init.ops = &refclk_scale_ops;
 	}
@@ -6717,6 +6732,9 @@ static int register_clocks(struct ad9361_rf_phy *phy)
 	ad9361_clk_register(phy, "-tx_sampl_clk", "-clktf_clk", NULL,
 		flags | CLK_IGNORE_UNUSED, TX_SAMPL_CLK);
 
+	ad9361_clk_register(phy, "-pl_intf_clk", "-tx_sampl_clk", NULL,
+		flags | CLK_IGNORE_UNUSED, PL_INTF_CLK);
+
 	ad9361_clk_register(phy, "-rx_rfpll_int", "-rx_refclk", NULL,
 		flags | CLK_IGNORE_UNUSED, RX_RFPLL_INT);
 

drivers/iio/adc/ad9361.h

@@ -33,6 +33,7 @@ enum ad9361_clocks {
 	TX_RFPLL_DUMMY,
 	RX_RFPLL,
 	TX_RFPLL,
+	PL_INTF_CLK,
 	NUM_AD9361_CLKS,
 };