Merge pull request radxa-pkg#271 from vamrs-feng/main

rockchip: overlays: nx5: add ov5647 support

arch/arm64/boot/dts/rockchip/overlays/Makefile

@@ -272,6 +272,10 @@ dtb-$(CONFIG_CPU_RK3568) += \
 	rock-3c-radxa-display-10hd.dtbo
 
 dtb-$(CONFIG_CLK_RK3588) += \
+	radxa-nx5-io-okdo-camera-5mp-cam0.dtbo \
+	radxa-nx5-io-okdo-camera-5mp-cam1.dtbo \
+	radxa-nx5-io-rpi-camera-v1p3-cam0.dtbo \
+	radxa-nx5-io-rpi-camera-v1p3-cam1.dtbo \
 	radxa-nx5-io-rpi-camera-v2-cam0.dtbo \
 	radxa-nx5-io-rpi-camera-v2-cam1.dtbo \
 	rk3588-disable-fiq-debugger.dtbo \

arch/arm64/boot/dts/rockchip/overlays/radxa-nx5-io-okdo-camera-5mp-cam0.dts

@@ -0,0 +1,217 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	metadata {
+		title ="Enable OKDO Camera 5MP on CAM0";
+		compatible = "radxa,nx5-io";
+		category = "camera";
+		exclusive = "csi2_dcphy0";
+		description = "Enable OKDO Camera 5MP on CAM0.";
+	};
+
+
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			clk_cam0_25m: external-camera-clock-25m {
+				compatible = "fixed-clock";
+				clock-frequency = <25000000>;
+				clock-output-names = "clk_cam0_25m";
+				#clock-cells = <0>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c4>;
+
+		__overlay__ {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-0 = <&i2c4m2_xfer>;
+
+			ov5647: ov5647@36 {
+				status = "okay";
+				compatible = "ovti,ov5647";
+				reg = <0x36>;
+				clocks = <&clk_cam0_25m>;
+				pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+				clock-names = "ext_cam_clk";
+				rockchip,camera-module-index = <1>;
+				rockchip,camera-module-facing = "back";
+				rockchip,camera-module-name = "OKDO-5MP";
+				rockchip,camera-module-lens-name = "default";
+
+				port {
+					ov5647_out0: endpoint {
+						remote-endpoint = <&mipidcphy0_in_ucam0>;
+						data-lanes = <1 2>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&mipi_dcphy0>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@3 {
+		target = <&csi2_dcphy0>;
+
+		__overlay__ {
+			status = "okay";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mipidcphy0_in_ucam0: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&ov5647_out0>;
+						data-lanes = <1 2>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					csidcphy0_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mipi0_csi2_input>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@4 {
+		target = <&mipi0_csi2>;
+
+		__overlay__ {
+			status = "okay";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mipi0_csi2_input: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&csidcphy0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mipi0_csi2_output: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&cif_mipi0_in0>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@5 {
+		target = <&rkcif>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@6 {
+		target = <&rkcif_mipi_lvds>;
+
+		__overlay__ {
+			status = "okay";
+
+			port {
+				cif_mipi0_in0: endpoint {
+					remote-endpoint = <&mipi0_csi2_output>;
+				};
+			};
+		};
+	};
+
+	fragment@7 {
+		target = <&rkcif_mipi_lvds_sditf>;
+
+		__overlay__ {
+			status = "okay";
+
+			port {
+				mipi_lvds_sditf: endpoint {
+					remote-endpoint = <&isp1_vir0>;
+				};
+			};
+		};
+	};
+
+	fragment@8 {
+		target = <&rkcif_mmu>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@9 {
+		target = <&isp1_mmu>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@10 {
+		target = <&rkisp1>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@11 {
+		target = <&rkisp1_vir0>;
+
+		__overlay__ {
+			status = "okay";
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				isp1_vir0: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&mipi_lvds_sditf>;
+				};
+			};
+		};
+	};
+};