fix: fix alchitry broken links

docs/FPGA/fpga_1.md

@@ -107,7 +107,7 @@ Now you should see that you have a project with several files:
 
 
 {: .important}
-You need to do your own self-study part to fill in the gaps and understand how the code works better by reading the <a href="https://alchitry.com/lucid" target="_blank">tutorials</a> provided by the original developer. The course handout also provides you some useful self-study materials. This document is only made to *complement* and *speed up* your self-study process, but it **doesn't mean** that you can forget about reading anything else. 
+You need to do your own self-study part to fill in the gaps and understand how the code works better by reading the <a href="https://alchitry.com/lucid_v1" target="_blank">tutorials</a> provided by the original developer. The course handout also provides you some useful self-study materials. This document is only made to *complement* and *speed up* your self-study process, but it **doesn't mean** that you can forget about reading anything else. 
 
 If you haven't read any tutorials about Lucid and Alchitry yet, here's some quick information: 
 * Under `Source`, thats where you will write **all** your script. `au_top.luc` is like the `main` script, so do not delete that. 
@@ -236,7 +236,7 @@ The `.acf` file defines input and output pins from the original schematic of `Al
 > 
 > An input pin with `pulldown` resistor will by default give a value of `0` if there's **no** input being supplied to prevent a *floating/undefined* input voltage. An input pin with a `pullup` resistorlikewise will give a value of `1` by default if there's no input being supplied at that port. It is useful to read abit about <a href="https://www.electronics-tutorials.ws/logic/pull-up-resistor.html" target="_blank">pull-down and pull-up resistors</a>  if you were to implement a unit from scratch like our Mini-Hardware Project.  
 
-This document will <span style="color:red; font-weight: bold;">not</span> teach you how to define more inputs for use on the `Br` board yet, or use the 7-segments to display numbers (it's an **anode** 7-seg, meaning you supply low `0` to turn the digit on). If you're interested to learn more, read the tutorial from the original author about <a href="https://alchitry.com/io-element" target="_blank">Io Element</a>
+This document will <span style="color:red; font-weight: bold;">not</span> teach you how to define more inputs for use on the `Br` board yet, or use the 7-segments to display numbers (it's an **anode** 7-seg, meaning you supply low `0` to turn the digit on). If you're interested to learn more, read the tutorial from the original author about <a href="https://alchitry.com/tutorials/lucid_v1/io-element/" target="_blank">Io Element</a>
 
 #### Turning LEDs `off`
 
@@ -441,7 +441,7 @@ By implementing this adder on the FPGA, we have learned:
 
 Now of course if you have read the documentation, you can simply implement an addition using a `+` in Lucid without having to resort to basic boolean logic because the interpreter will implement the addition for you. Either way, the hardware circuitry is still the same. If you use `+`, then you are describing the **functionality** of the circuit. Vivado will then build the corresponding hardware unit (logically) by programming the FPGA. If you describe the adder's schematic explicitly, then you are doing what Vivado did when synthesizing a `+`. Either way, the final functionality is the **same**, which is *to add*.
 
-You are highly encouraged to read <a href="https://alchitry.com/your-first-fpga-project" target="_blank">this tutorial</a>  to enhance your understanding afterwards. 
+You are highly encouraged to read <a href="https://alchitry.com/tutorials/lucid_v1/your-first-fpga-project/" target="_blank">this tutorial</a>  to enhance your understanding afterwards. 
 
 {: .important-title}
 > About Using External IO

docs/FPGA/fpga_2.md

@@ -88,7 +88,7 @@ module seq_plus_two (
 ``` 
 
 {: .note}
-`.clk(clk)` means to connect the `clk` signal of the `dff` with the `clk` signal of `seq_plus_two` (supplied as input from the on-board clock hardware).* There one other way to declare the `clk` and the `rst` signal before the always block -- a <a href="https://alchitry.com/synchronous-logic" target="_blank">nested</a>  way. It works the same, just probably is easier to type when you have many modules to declare that receives the same `clk` and `rst` signal. 
+`.clk(clk)` means to connect the `clk` signal of the `dff` with the `clk` signal of `seq_plus_two` (supplied as input from the on-board clock hardware).* There one other way to declare the `clk` and the `rst` signal before the always block -- a <a href="https://alchitry.com/tutorials/lucid_v1/synchronous-logic/" target="_blank">nested</a>  way. It works the same, just probably is easier to type when you have many modules to declare that receives the same `clk` and `rst` signal. 
 
 The `dff` has **two** important terminals: `.d` for **input** and `.q` for **output**. We simply have to **connect** them with the adder. Let's declare the adder module as well and connect them:
 
@@ -172,7 +172,7 @@ Now you should be able to see that the LEDs are lighted up and they resembles bi
 >
 > When you click the reset button, it will **not** restart the addition back from `0` again! Can you guess why? Don't worry about it for now. We will tackle this problem in Part 3  of the tutorial.
 
-Also, to **enhance** your understanding in creating synchronous / sequential logic modules, **it is important for you** to read <a href="https://alchitry.com/synchronous-logic" target="_blank">this</a>  tutorial written by the original author. 
+Also, to **enhance** your understanding in creating synchronous / sequential logic modules, **it is important for you** to read <a href="https://alchitry.com/tutorials/lucid_v1/synchronous-logic/" target="_blank">this</a>  tutorial written by the original author. 
 
 
 ## Creating a Finite State Machine 
@@ -294,7 +294,7 @@ As usual, declare `seq_plus_vary` instance in `au_top.luc` with the **slower clo
 You can download `seq_plus_vary.luc` <a href="https://github.com/natalieagus/SampleAlchitryProjects/blob/master/GettingStartedWithFPGA/source/seq_plus_vary.luc" target="_blank">here</a>.
 ## Summary
 
-In this document, we are given a glimpse on how to create a synchronous / sequential logic circuit. Please also read <a href="https://alchitry.com/synchronous-logic" target="_blank">this tutorial</a> to enhance your understanding. We were also introduced into two new types: `dff` and `fsm`. You are recommended to read more about FSM <a href="https://alchitry.com/roms-and-fsms" target="_blank">here</a>. 
+In this document, we are given a glimpse on how to create a synchronous / sequential logic circuit. Please also read <a href="https://alchitry.com/tutorials/lucid_v1/synchronous-logic/" target="_blank">this tutorial</a> to enhance your understanding. We were also introduced into two new types: `dff` and `fsm`. You are recommended to read more about FSM <a href="https://alchitry.com/tutorials/lucid_v1/roms-and-fsms/" target="_blank">here</a>. 
 
 It is important to always remind yourself that the `always` block contains the **hardware description** of your device. It is **NOT** a piece of code that is sequentially executed by a processor like our usual Python and C code (there's no processor here!). They're *interpreted* by Xilinx and Alchitry tools sequentially, but not evaluated sequentially. **You should always remind yourself that everything in an always block as being evaluated continuously.** 
 

docs/FPGA/fpga_3.md

@@ -26,7 +26,7 @@ This is the final document in the series. It mainly shows how to handle I/O unit
 {: .note}
 We won't be discussing how to use the 7 segment here. 
 
-There are lots of <a href="https://alchitry.com/io-element" target="_blank">online tutorial</a> on how to operate a 7-segment. **The Io Element Base template** itself also already contain a sample on how to use the 7-segment, so please study it. 
+There are lots of <a href="https://alchitry.com/tutorials/lucid_v1/io-element/" target="_blank">online tutorial</a> on how to operate a 7-segment. **The Io Element Base template** itself also already contain a sample on how to use the 7-segment, so please study it. 
 
 ## External 7 Segment
 If you do buy an external 7-segment, please take note of the required **supply voltage**. Also pay attention whether you're buying a <a href="https://www.electronics-tutorials.ws/blog/7-segment-display-tutorial.html" target="_blank">cathode or anode</a>  7-segment. 
@@ -97,7 +97,7 @@ Bottomline is that external inputs are **unreliable**, and can be disastrous if
 
 Normally, we can entirely avoid the **metastability** and **desynchronisation** problem using the built-in component provided by AlchitryLab: `reset_conditioner`.
 
-The `reset_conditioner` in `au_top.luc` **synchronises** the reset signal **with the actual FPGA clock** so that all synchronous units in the FPGA will come out of reset at once, so that there won't be a case where some `dff` stay reset one cycle longer than the other.  You can read more about `reset_conditioner`  at the end of <a href="https://alchitry.com/synchronous-logic" target="_blank">this</a> tutorial and <a href="https://learn.sparkfun.com/tutorials/external-io-and-metastability/all" target="_blank">this</a> tutorial as well.
+The `reset_conditioner` in `au_top.luc` **synchronises** the reset signal **with the actual FPGA clock** so that all synchronous units in the FPGA will come out of reset at once, so that there won't be a case where some `dff` stay reset one cycle longer than the other.  You can read more about `reset_conditioner`  at the end of <a href="https://alchitry.com/tutorials/lucid_v1/synchronous-logic/" target="_blank">this</a> tutorial and <a href="https://learn.sparkfun.com/tutorials/external-io-and-metastability/all" target="_blank">this</a> tutorial as well.
 
 For our `seq_plus_two.luc` unit, we used a custom clock and a separate manual reset from the rest of the units implemented in the FPGA.  While for this case seems fine (because it works for the **limited** number of times you tested it manually), it is a bad idea because if you have a more complicated system **it can be** **disastrous**:
  * If you manually reset each and every one of them without any kind of conditioner unit, then there's no way to ensure that all units come out of the reset at the same time. 
@@ -526,11 +526,11 @@ Input pins with default <code>pulldown</code> resistor will produce a <code>0</c
 This document builds up on some of the things we learned before in Part 1 and 2, and it mainly focuses on how to use external I/O devices and reset the whole system properly. You may find the complete project used in all three parts of this introduction to FPGA <a href="https://github.com/natalieagus/SampleAlchitryProjects" target="_blank">here</a>.  
 
 You are recommended to read further on (if they're applicable to your project of course) :
-1.  **How <a href="https://alchitry.com/io-element" target="_blank">7-Segment works</a>** (you can learn using the onboard 7-segment on Alchitry Io first before buying external units). **7-Segment component** is useful to display numbers, e.g: display score, time left, etc. 
+1.  **How <a href="https://alchitry.com/tutorials/lucid_v1/io-element/" target="_blank">7-Segment works</a>** (you can learn using the onboard 7-segment on Alchitry Io first before buying external units). **7-Segment component** is useful to display numbers, e.g: display score, time left, etc. 
 
 2. **How LED Strips work** (e.g: WS2812B, or SK6812 LEDs). You can refer to online tutorials like  <a href="https://vivonomicon.com/2018/12/24/learning-how-to-fpga-with-neopixel-leds/" target="_blank">this</a> one. Then read the [**datasheet**](https://www.dropbox.com/s/7kj6aa9n6817tid/WS2812.pdf?dl=0), see here for WS2812B datasheet so you understand how to send the low bits and the high bits to encode an LED color. We have some sample LED writers that's Au and WS2812B compatible <a href="https://github.com/natalieagus/ws2812b" target="_blank">here</a>  to get you started. 
 
-3. How you can utilize another powerful **storage device:** the **default RAM component**. You can find the <a href="https://alchitry.com/hello-your_name_here" target="_blank"> tutorial</a> written by the original author here (there's single-port and dual-port RAM). 
+3. How you can utilize another powerful **storage device:** the **default RAM component**. You can find the <a href="https://alchitry.com/tutorials/lucid_v1/hello-your-name-here/" target="_blank"> tutorial</a> written by the original author here (there's single-port and dual-port RAM). 
 
 	 <strong>RAM component</strong> is <strong>especially useful</strong> if you need to store a **large** amount of data <>, e.g data to be rendered out to large (32x32 or 64x32, etc) LED matrices. It is convenient to use the `dff` for small data storages, but you will run out of logic units real fast if you were to create thousands of dffs (not to mention the bizzare amount of time needed to compile the code). 
 

docs/FPGA/fpga_applesilicon.md

@@ -62,7 +62,7 @@ Ensure that your desktop looks like this. If it doesn't it means that what you h
 
 ### Shared Directory 
 
-After compiling your code, you will need to load the binary to your FPGA. There's no USB passthrough with the VM (it's not the usual QEMU), so you will need to migrate `PROJECT_PATH/work/alchitry.bin` to your host machine and flash it to your FPGA using [Alchitry Loader part of the Alchitry Labs](https://new.alchitry.com/Alchitry-Labs-V2/download.html).
+After compiling your code, you will need to load the binary to your FPGA. There's no USB passthrough with the VM (it's not the usual QEMU), so you will need to migrate `PROJECT_PATH/work/alchitry.bin` to your host machine and flash it to your FPGA using [Alchitry Loader part of the Alchitry Labs](https://alchitry.com/Alchitry-Labs-V2/download.html).
 
 <img src="{{ site.baseurl }}/docs/FPGA/images/fpga_applesilicon/2024-03-18-14-34-46.png"  class="center_full no-invert"/>
 

docs/FPGA/index.md

@@ -30,10 +30,10 @@ If you're looking for 1D project sample for 50.002, checkout [this Counter Game
 
 
 **More material that are recommended:**
-1. [Background tutorial](https://alchitry.com/background)
-2. [Your First FPGA Project](https://alchitry.com/your-first-fpga-project) and [external IO setup](https://learn.sparkfun.com/tutorials/external-io-and-metastability/all) 
-3. [Synchronous Logic](https://alchitry.com/synchronous-logic) (Related to Week 3 materials)
-4. [Io Element Project](https://alchitry.com/io-element)
-5. [ROM and FSMs Project](https://alchitry.com/roms-and-fsms) (Related to Week 2-5 materials)
-6. [Basic CPU](https://alchitry.com/hello-your_name_here)  (Related to Beta CPU)
-7. [DDR3 RAM](https://alchitry.com/ddr3-memory) (intermediate) 
+1. [Background tutorial](https://alchitry.com/tutorials/background/)
+2. [Your First FPGA Project](https://alchitry.com/tutorials/lucid_v1/your-first-fpga-project/) and [external IO setup](https://learn.sparkfun.com/tutorials/external-io-and-metastability/all) 
+3. [Synchronous Logic](https://alchitry.com/tutorials/lucid_v1/synchronous-logic/) (Related to Week 3 materials)
+4. [Io Element Project](https://alchitry.com/tutorials/lucid_v1/io-element/)
+5. [ROM and FSMs Project](https://alchitry.com/tutorials/lucid_v1/roms-and-fsms/) (Related to Week 2-5 materials)
+6. [Basic CPU](https://alchitry.com/tutorials/lucid_v1/hello-your-name-here/)  (Related to Beta CPU)
+7. [DDR3 RAM](https://alchitry.com/tutorials/lucid_v1/ddr3-memory/) (intermediate) 

docs/Labs/lab3-part1.md

@@ -22,7 +22,7 @@ Modified by: Natalie Agus (2024)
 {: .no_toc}
 
 {: .warning}
-Before this lab, you are required to [complete this very basic FPGA tutorial](https://natalieagus.github.io/50002/fpga/fpga_1) we wrote and perhaps the official [Getting-Started-With-FPGA tutorial](https://alchitry.com/your-first-fpga-project) by Alchitry lab. Please **come prepared** and bring your FPGA + laptops where Vivado + Alchitry Lab is installed. At least one person in each team should have a laptop that can run Vivado and bring the FPGA. 
+Before this lab, you are required to [complete this very basic FPGA tutorial](https://natalieagus.github.io/50002/fpga/fpga_1) we wrote and perhaps the official [Getting-Started-With-FPGA tutorial](https://alchitry.com/tutorials/lucid_v1/your-first-fpga-project/) by Alchitry lab. Please **come prepared** and bring your FPGA + laptops where Vivado + Alchitry Lab is installed. At least one person in each team should have a laptop that can run Vivado and bring the FPGA. 
 
 
 ## Starter Code

docs/Software/m_cacheissues.md

@@ -237,11 +237,13 @@ Random replacement policy is the simplest to implement as it does not require mu
 
 ## [The Cache Block Size](https://www.youtube.com/watch?v=2OARjqLK4io&t=1860s)
 
-We can further improve cache performance by **increasing the capacity of each cache line**. We can **fetch  `B` words of data at a time**, and this is especially useful if there's high locality of reference.  The figure below illustrates a cache line with block size of 4:
+We can further improve cache performance by **increasing the capacity of each cache line**. We can **fetch  `B` words of data at a time**, and this is especially useful if there's high locality of reference.  The figure below illustrates a cache with a single cache line and a block size of 4:
 
 
 <img src="{{ site.baseurl }}/assets/images/notes/cache-word-block.png"  class="center_seventy"/>
 
+{:.highlight}
+Apply this knowledge if we have N cache lines and block size of 4: how many `TAG`, `k`, and `b` bits are there? 
 
 {: .new-title}
 > Cache Block Size