feat: add operation summaries

natalieagus · Dec 4, 2024 · 7fc0d80 · 7fc0d80
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diff --git a/docs/Hardware/i_betacpu.md b/docs/Hardware/i_betacpu.md
@@ -227,10 +227,12 @@ In our Lab however, the output signal of the control unit is 18 bits long. We do
 ## Beta Datapaths
 
 The $$\beta$$ datapath can be reprogrammed by setting the appropriate control signals depending on the current instruction's `OPCODE`. In general, we can separate the instructions into four categories, and explain the datapath for each:
-* The `OP` datapath (Type 1)
-* The `OPC` datapath (Type 2)
-* Memory access datapath (Type 2)
-* Control transfer datapath  (Type 2)
+* The `OP` datapath (Type 1): ADD, SUB, MUL, DIV, SHL, SHR, SRA, CMPEQ, CMPLT, CMPLTE, AND, OR, XOR  (13 operations)
+* The `OPC` datapath (Type 2): ADDC, SUBC, MULC, DIVC, SHLC, SHRC, SRAC, CMPEQC, CMPLTC, CMPLTEC, ANDC, ORC, XORC (13 operations)
+* Memory access datapath (Type 2): ST, LD, LDR (3 operations)
+* Control transfer datapath  (Type 2): JMP, BNE, BEQ (3 operations)
+
+**Total: 32 operations**.
 
 ## Basic Operation Datapath
 ### [OP datapath](https://www.youtube.com/watch?v=4T9MR8BSzt0&t=1662s)

diff --git a/docs/Labs/lab4.md b/docs/Labs/lab4.md
@@ -25,7 +25,7 @@ Singapore University of Technology and Design
 
 Please clone the starter code from this repository, then **open** it with Alchitry Lab. 
 ```
-TBC
+git clone https://github.com/natalieagus/50002-lab4-beta.git
 ```
 
 Then, you shall **paste** the implementation of your 32-bit ALU unit created in Lab 3: ALU. Be sure to include **all** files required by your `alu.luc`.
@@ -60,8 +60,8 @@ The goal of this lab is to build a **fully** functional 32-bit Beta Processor on
 * (Part A) **PC** Unit: containing the PC register and all necessary components to support the ISA
 * (Part B) **REGFILE** Unit: containing 32 32-bit registers, WASEL, and RA2SEL mux, plus circuitry to compute Z
 * (Part C) **CONTROL** Unit: containing the ROM and necessary components to produce all Beta control signals given an `OPCODE`
-* **ALU+WDSEL** Unit: containing the ALU and WDSEL, ASEL, BSEL muxes (**given to you**)
-* (Part D) Assemble the entire Beta CPU using all subcomponents above
+* (Part D)  **ALU+WDSEL** Unit: containing the ALU and WDSEL, ASEL, BSEL muxes 
+* Finally, assemble the entire Beta CPU using all subcomponents above
 
 <img src="/50002/assets/contentimage/lab4/beta_lab.png"  class="center_seventy"/><br>