Skip to content

Commit

Permalink
applications: sdp: mspi: Dummy cycles fix
Browse files Browse the repository at this point in the history 
Fixed dummy cycles implementation.
Changed dummy cycles limit from 32 to UINT32_MAX.

Signed-off-by: Michal Frankiewicz <[email protected]>
  • Loading branch information
@mif1-nordic
mif1-nordic committed Feb 3, 2025
1 parent 0e0d435 commit 2259040
Show file tree
Hide file tree
Showing 4 changed files with 185 additions and 129 deletions.
10 changes: 9 additions & 1 deletion applications/sdp/mspi/src/hrt/hrt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,11 @@ static void hrt_tx(volatile hrt_xfer_data_t *xfer_data, uint8_t frame_width, boo
SHIFTCNTB_VALUE(xfer_data->penultimate_word_clocks);
nrf_vpr_csr_vio_shift_ctrl_buffered_set(&xfer_shift_ctrl);
default: /* Intentional fallthrough */
xfer_data->vio_out_set(((uint32_t *)xfer_data->data)[i]);
if (xfer_data->data == NULL) {
xfer_data->vio_out_set(0);
} else {
xfer_data->vio_out_set(((uint32_t *)xfer_data->data)[i]);
}
}

if ((i == 0) && (!*counter_running)) {
Expand Down Expand Up @@ -156,6 +160,10 @@ void hrt_write(hrt_xfer_t *hrt_xfer_params)
/* Transfer address */
hrt_tx(&hrt_xfer_params->xfer_data[HRT_FE_ADDRESS], hrt_xfer_params->bus_widths.address,
&counter_running, hrt_xfer_params->counter_value);
/* Transfer dummy cycles */
hrt_tx(&hrt_xfer_params->xfer_data[HRT_FE_DUMMY_CYCLES],
hrt_xfer_params->bus_widths.dummy_cycles, &counter_running,
hrt_xfer_params->counter_value);
/* Transfer data */
hrt_tx(&hrt_xfer_params->xfer_data[HRT_FE_DATA], hrt_xfer_params->bus_widths.data,
&counter_running, hrt_xfer_params->counter_value);
Expand Down
6 changes: 5 additions & 1 deletion applications/sdp/mspi/src/hrt/hrt.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@
typedef enum {
HRT_FE_COMMAND,
HRT_FE_ADDRESS,
HRT_FE_DUMMY_CYCLES,
HRT_FE_DATA,
HRT_FE_MAX
} hrt_frame_element_t;
Expand All @@ -32,6 +33,7 @@ typedef enum {
typedef struct {
uint8_t command;
uint8_t address;
uint8_t dummy_cycles;
uint8_t data;
} hrt_xfer_bus_widths_t;

Expand Down Expand Up @@ -78,7 +80,9 @@ typedef struct {
/** @brief Data for all transfer parts */
hrt_xfer_data_t xfer_data[HRT_FE_MAX];

/** @brief Bus widths for different transfer parts (command, address, and data). */
/** @brief Bus widths for different transfer parts (command, address, dummy_cycles, and
* data).
*/
hrt_xfer_bus_widths_t bus_widths;

/** @brief Timer value, used for setting clock frequency
Expand Down
216 changes: 120 additions & 96 deletions applications/sdp/mspi/src/hrt/hrt.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,84 +16,92 @@ hrt_tx:
sw a2,0(sp)
sw a3,4(sp)
beq a4,zero,.L1
slli a3,a1,12
slli s0,a1,12
li a4,126976
and a3,a3,a4
and s0,s0,a4
li a4,32
div a4,a4,a1
mv s0,a0
mv a5,a0
addi a4,a4,-1
andi a4,a4,63
or a4,a4,a3
or a4,a4,s0
ori a4,a4,1024
#APP
csrw 3019, a4
#NO_APP
li s1,0
.L3:
lw a4,4(s0)
bltu s1,a4,.L9
lw a4,4(a5)
bltu s1,a4,.L10
.L1:
lw ra,20(sp)
lw s0,16(sp)
lw s1,12(sp)
addi sp,sp,24
jr ra
.L9:
lw a4,4(s0)
li a1,1
.L10:
lw a4,4(a5)
li a2,1
sub a4,a4,s1
beq a4,a1,.L4
li a1,2
beq a4,a1,.L5
beq a4,a2,.L4
li a2,2
beq a4,a2,.L5
.L6:
lw a1,16(s0)
lw a4,0(s0)
slli a0,s1,2
sw a3,8(sp)
add a4,a4,a0
lw a0,0(a4)
jalr a1
j .L12
lw a4,0(a5)
bne a4,zero,.L8
lw a4,16(a5)
sw a5,8(sp)
li a0,0
j .L14
.L4:
lbu a4,8(s0)
sw a3,8(sp)
lbu a4,8(a5)
addi a4,a4,-1
andi a4,a4,63
or a4,a4,a3
or a4,a4,s0
ori a4,a4,1024
#APP
csrw 3019, a4
#NO_APP
lw a4,16(s0)
lw a0,12(s0)
lw a4,16(a5)
lw a0,12(a5)
sw a5,8(sp)
.L14:
jalr a4
.L12:
lw a3,8(sp)
bne s1,zero,.L8
lw a5,0(sp)
lbu a4,0(a5)
bne a4,zero,.L8
lw a5,4(sp)
.L13:
lw a5,8(sp)
bne s1,zero,.L9
lw a4,0(sp)
lbu a4,0(a4)
bne a4,zero,.L9
lw a4,4(sp)
#APP
csrw 2005, a5
csrw 2005, a4
#NO_APP
lw a5,0(sp)
lw a3,0(sp)
li a4,1
sb a4,0(a5)
.L8:
sb a4,0(a3)
.L9:
addi s1,s1,1
j .L3
.L5:
lbu a4,9(s0)
lbu a4,9(a5)
addi a4,a4,-1
andi a4,a4,63
or a4,a4,a3
or a4,a4,s0
ori a4,a4,1024
#APP
csrw 3019, a4
#NO_APP
j .L6
.L8:
lw a2,16(a5)
lw a4,0(a5)
slli a1,s1,2
sw a5,8(sp)
add a4,a4,a1
lw a0,0(a4)
jalr a2
j .L13
.size hrt_tx, .-hrt_tx
.section .text.hrt_write,"ax",@progbits
.align 1
Expand All @@ -103,138 +111,154 @@ hrt_write:
addi sp,sp,-16
sw s0,8(sp)
sw ra,12(sp)
lhu a5,70(a0)
mv s0,a0
sb zero,3(sp)
lhu a5,90(a0)
#APP
csrw 3009, a5
#NO_APP
lw a5,4(a0)
beq a5,zero,.L14
lbu a3,60(a0)
li a5,0
.L15:
addi a4,a0,4
li a3,4
.L17:
lw a2,0(a4)
bne a2,zero,.L16
addi a5,a5,1
andi a5,a5,0xff
addi a4,a4,20
bne a5,a3,.L17
li a5,3
.L16:
li a4,1
beq a5,a4,.L18
li a4,3
beq a5,a4,.L19
li a4,0
bne a5,zero,.L20
lbu a4,80(s0)
.L20:
#APP
csrw 2000, 2
#NO_APP
lhu a4,64(s0)
lhu a3,84(s0)
#APP
csrr a2, 2003
#NO_APP
li a1,-65536
and a2,a2,a1
or a4,a4,a2
or a3,a3,a2
#APP
csrw 2003, a4
csrw 2003, a3
csrw 3011, 0
#NO_APP
li a2,2031616
slli a4,a3,16
and a4,a4,a2
ori a4,a4,4
slli a3,a4,16
and a3,a3,a2
ori a3,a3,4
#APP
csrw 3043, a4
csrw 3043, a3
#NO_APP
li a4,20
mul a5,a5,a4
li a3,20
mul a5,a5,a3
li a2,1
add a5,s0,a5
lw a4,4(a5)
beq a4,a2,.L17
lw a3,4(a5)
beq a3,a2,.L21
li a2,2
beq a4,a2,.L18
beq a3,a2,.L22
li a5,32
div a5,a5,a3
j .L33
.L14:
lw a5,24(a0)
beq a5,zero,.L16
lbu a3,61(a0)
li a5,1
j .L15
.L16:
lbu a3,62(a0)
li a5,2
j .L15
.L17:
div a5,a5,a4
j .L39
.L18:
lbu a4,81(s0)
j .L20
.L19:
lbu a4,83(s0)
j .L20
.L21:
lbu a5,8(a5)
.L33:
.L39:
#APP
csrw 3022, a5
#NO_APP
lbu a4,66(s0)
lbu a4,86(s0)
li a5,1
sll a5,a5,a4
lbu a4,68(s0)
lbu a4,88(s0)
slli a5,a5,16
srli a5,a5,16
bne a4,zero,.L21
bne a4,zero,.L25
#APP
csrc 3008, a5
#NO_APP
.L22:
lhu a3,64(s0)
lbu a1,60(s0)
.L26:
lhu a3,84(s0)
lbu a1,80(s0)
addi a2,sp,3
mv a0,s0
call hrt_tx
lhu a3,64(s0)
lbu a1,61(s0)
lhu a3,84(s0)
lbu a1,81(s0)
addi a2,sp,3
addi a0,s0,20
call hrt_tx
lhu a3,64(s0)
lbu a1,62(s0)
lhu a3,84(s0)
lbu a1,82(s0)
addi a2,sp,3
addi a0,s0,40
call hrt_tx
lbu a5,69(s0)
beq a5,zero,.L23
.L24:
lhu a3,84(s0)
lbu a1,83(s0)
addi a2,sp,3
addi a0,s0,60
call hrt_tx
lbu a5,89(s0)
beq a5,zero,.L27
.L28:
#APP
csrr a5, 3022
#NO_APP
andi a5,a5,0xff
bne a5,zero,.L24
bne a5,zero,.L28
#APP
csrw 2010, 0
#NO_APP
.L23:
.L27:
li a5,16384
addi a5,a5,1
#APP
csrw 3019, a5
csrw 3017, 0
csrw 2000, 0
#NO_APP
lbu a5,67(s0)
bne a5,zero,.L13
lbu a4,66(s0)
lbu a5,87(s0)
bne a5,zero,.L15
lbu a4,86(s0)
li a5,1
sll a5,a5,a4
lbu a4,68(s0)
lbu a4,88(s0)
slli a5,a5,16
srli a5,a5,16
bne a4,zero,.L26
bne a4,zero,.L30
#APP
csrs 3008, a5
#NO_APP
.L13:
.L15:
lw ra,12(sp)
lw s0,8(sp)
addi sp,sp,16
jr ra
.L18:
.L22:
lbu a5,9(a5)
j .L33
.L21:
j .L39
.L25:
#APP
csrs 3008, a5
#NO_APP
j .L22
.L26:
j .L26
.L30:
#APP
csrc 3008, a5
#NO_APP
j .L13
j .L15
.size hrt_write, .-hrt_write
Loading

0 comments on commit 2259040

Please sign in to comment.