applications: sdp: mspi: Add new SDP MSPI application

Application for FLPR core to communicate with SDP MSPI driver.

Signed-off-by: Jakub Zymelka <[email protected]>

applications/sdp/mspi/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(sdp_mspi)
+
+#sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+#sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+#sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+
+target_sources(app PRIVATE src/main.c)
+# target_sources(app PRIVATE src/hrt/hrt.s)
+
+#add_dependencies(app asm_check)

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,46 @@
+# Single-threaded
+CONFIG_MULTITHREADING=n
+CONFIG_KERNEL_MEM_POOL=n
+CONFIG_LOG=n
+
+# Drivers and peripherals
+CONFIG_I2C=n
+CONFIG_WATCHDOG=n
+CONFIG_GPIO=n
+CONFIG_PINCTRL=n
+CONFIG_SPI=n
+CONFIG_SERIAL=n
+CONFIG_FLASH=n
+
+# Power management
+CONFIG_PM=n
+
+# Interrupts
+CONFIG_DYNAMIC_INTERRUPTS=n
+CONFIG_IRQ_OFFLOAD=n
+CONFIG_GEN_SW_ISR_TABLE=n
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+CONFIG_FPU=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
+
+# Console
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_STDOUT_CONSOLE=n
+CONFIG_PRINTK=n
+CONFIG_EARLY_CONSOLE=n
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
+
+# No timer support in the kernel
+CONFIG_SYS_CLOCK_EXISTS=n
+
+CONFIG_OUTPUT_DISASSEMBLY=y
+CONFIG_COMMON_LIBC_MALLOC=n

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@2003c000 {
+				reg = <0x2003c000 0x0800>;
+			};
+
+			sram_rx: memory@2003c800 {
+				reg = <0x2003c800 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_rram {
+	reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_sram {
+	reg = <0x2003d000 DT_SIZE_K(12)>;
+	ranges = <0x0 0x2003d000 0x3000>;
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+	interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
+	nordic,tasks = <1>;
+	nordic,tasks-mask = <0x00010000>;
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&gpiote20 {
+	status = "disabled";
+};
+
+&gpiote30 {
+	status = "disabled";
+};
+
+&grtc {
+	status = "disabled";
+};
+
+&uart20 {
+	status = "disabled";
+};
+
+&uart30 {
+	status = "disabled";
+};
+
+&pwm20 {
+	status = "disabled";
+};

applications/sdp/mspi/prj.conf

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+CONFIG_MBOX=y
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

applications/sdp/mspi/sample.yaml

@@ -0,0 +1,14 @@
+sample:
+  name: SDP GPIO application
+  description: SDP GPIO application
+common:
+  integration_platforms:
+    - nrf54l15dk/nrf54l15/cpuflpr
+tests:
+  applications.sdp.mspi:
+    build_only: true
+    sysbuild: true
+    platform_allow: nrf54l15dk/nrf54l15/cpuflpr
+    tags: ci_build sysbuild mspi
+    # required_snippets:
+    #   - sdp-mspi

applications/sdp/mspi/src/hrt/hrt.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+#include "hrt.h"
+#include <hal/nrf_vpr_csr_vio.h>
+
+extern volatile uint16_t irq_arg;
+
+void hrt_set_bits(void)
+{
+	uint16_t outs = nrf_vpr_csr_vio_out_get();
+
+	nrf_vpr_csr_vio_out_set(outs | irq_arg);
+}
+
+void hrt_clear_bits(void)
+{
+	uint16_t outs = nrf_vpr_csr_vio_out_get();
+
+	nrf_vpr_csr_vio_out_set(outs & ~irq_arg);
+}
+
+void hrt_toggle_bits(void)
+{
+	nrf_vpr_csr_vio_out_toggle_set(irq_arg);
+}

applications/sdp/mspi/src/hrt/hrt.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#ifndef _HRT_H__
+#define _HRT_H__
+
+void hrt_set_bits(void);
+
+void hrt_clear_bits(void);
+
+void hrt_toggle_bits(void);
+
+#endif /* _HRT_H__ */

applications/sdp/mspi/src/hrt/hrt.s

@@ -0,0 +1,55 @@
+	.file	"hrt.c"
+	.option nopic
+	.attribute arch, "rv32e1p9_m2p0_c2p0_zicsr2p0"
+	.attribute unaligned_access, 0
+	.attribute stack_align, 4
+	.text
+	.section	.text.hrt_set_bits,"ax",@progbits
+	.align	1
+	.globl	hrt_set_bits
+	.type	hrt_set_bits, @function
+hrt_set_bits:
+ #APP
+	csrr a4, 3008
+ #NO_APP
+	lui	a5,%hi(irq_arg)
+	lhu	a5,%lo(irq_arg)(a5)
+	or	a5,a5,a4
+	slli	a5,a5,16
+	srli	a5,a5,16
+ #APP
+	csrw 3008, a5
+ #NO_APP
+	ret
+	.size	hrt_set_bits, .-hrt_set_bits
+	.section	.text.hrt_clear_bits,"ax",@progbits
+	.align	1
+	.globl	hrt_clear_bits
+	.type	hrt_clear_bits, @function
+hrt_clear_bits:
+ #APP
+	csrr a4, 3008
+ #NO_APP
+	lui	a5,%hi(irq_arg)
+	lhu	a5,%lo(irq_arg)(a5)
+	not	a5,a5
+	and	a5,a5,a4
+	slli	a5,a5,16
+	srli	a5,a5,16
+ #APP
+	csrw 3008, a5
+ #NO_APP
+	ret
+	.size	hrt_clear_bits, .-hrt_clear_bits
+	.section	.text.hrt_toggle_bits,"ax",@progbits
+	.align	1
+	.globl	hrt_toggle_bits
+	.type	hrt_toggle_bits, @function
+hrt_toggle_bits:
+	lui	a5,%hi(irq_arg)
+	lhu	a5,%lo(irq_arg)(a5)
+ #APP
+	csrw 3024, a5
+ #NO_APP
+	ret
+	.size	hrt_toggle_bits, .-hrt_toggle_bits