applications: sdp: mspi: Add IPC solution to SDP MSPI application

Add IPC solution based on icmsg to application for FLPR core to communicate with SDP MSPI driver. Signed-off-by: Jakub Zymelka <[email protected]>
nrfconnect · Dec 2, 2024 · e775e14 · e775e14
1 parent debe97b
commit e775e14
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Showing 7 changed files with 221 additions and 60 deletions.
diff --git a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay
@@ -4,6 +4,58 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@2003c000 {
+				reg = <0x2003c000 0x0800>;
+			};
+
+			sram_rx: memory@2003c800 {
+				reg = <0x2003c800 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_rram {
+	reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_sram {
+	reg = <0x2003d000 DT_SIZE_K(12)>;
+	ranges = <0x0 0x2003d000 0x3000>;
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+	interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
+	nordic,tasks = <1>;
+	nordic,tasks-mask = <0x00010000>;
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
 &gpio0 {
 	status = "disabled";
 };

diff --git a/applications/sdp/mspi/prj.conf b/applications/sdp/mspi/prj.conf
@@ -1 +1,3 @@
 CONFIG_MBOX=y
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
diff --git a/applications/sdp/mspi/sample.yaml b/applications/sdp/mspi/sample.yaml
@@ -5,11 +5,10 @@ common:
   integration_platforms:
     - nrf54l15dk/nrf54l15/cpuflpr
 tests:
-  applications.sdp.mspi.icmsg:
+  applications.sdp.mspi:
     build_only: true
     sysbuild: true
     platform_allow: nrf54l15dk/nrf54l15/cpuflpr
     tags: ci_build sysbuild mspi
-    extra_configs:
-      - CONFIG_IPC_SERVICE=y
-      - CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
+    required_snippets:
+      - sdp-mspi
diff --git a/applications/sdp/mspi/src/hrt/hrt.c b/applications/sdp/mspi/src/hrt/hrt.c
@@ -6,8 +6,7 @@
 #include "hrt.h"
 #include <hal/nrf_vpr_csr_vio.h>
 #include <hal/nrf_vpr_csr_vtim.h>
-
-#define TOP 4
+#include <drivers/mspi/nrfe_mspi.h>
 
 void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
 			  uint8_t word_size, bool ce_enable_state, bool hold_ce)
@@ -17,13 +16,15 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
 	/* Configuration step */
 	uint16_t dir = nrf_vpr_csr_vio_dir_get();
 
-	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(CS_PIN) |
-				PIN_DIR_OUT_MASK(SCLK_PIN));
+	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
 
 	uint16_t out = nrf_vpr_csr_vio_out_get();
 
-	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_HIGH_MASK(CS_PIN) |
-				PIN_OUT_LOW_MASK(SCLK_PIN));
+	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
 
 	nrf_vpr_csr_vio_mode_out_t out_mode = {
 		.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
@@ -60,8 +61,9 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
 
 	/* Enable CS */
 	out = nrf_vpr_csr_vio_out_get();
-	out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
-	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
+	out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+			       : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
 	nrf_vpr_csr_vio_out_set(out);
 
 	/* Start counter */
@@ -83,9 +85,11 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
 	/* Deselect slave */
 	if (!hold_ce) {
 		out = nrf_vpr_csr_vio_out_get();
-		out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
-		out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
-		out |= PIN_OUT_LOW_MASK(SCLK_PIN);
+		out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+			 PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+		out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+				       : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+		out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
 		nrf_vpr_csr_vio_out_set(out);
 	}
 
@@ -102,15 +106,21 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
 	/* Configuration step */
 	uint16_t dir = nrf_vpr_csr_vio_dir_get();
 
-	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(D1_PIN) |
-				PIN_DIR_OUT_MASK(D2_PIN) | PIN_DIR_OUT_MASK(D3_PIN) |
-				PIN_DIR_OUT_MASK(CS_PIN) | PIN_DIR_OUT_MASK(SCLK_PIN));
+	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
 
 	uint16_t out = nrf_vpr_csr_vio_out_get();
 
-	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_LOW_MASK(D1_PIN) |
-				PIN_OUT_LOW_MASK(D2_PIN) | PIN_OUT_LOW_MASK(D3_PIN) |
-				PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_LOW_MASK(SCLK_PIN));
+	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
+				PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
 
 	nrf_vpr_csr_vio_mode_out_t out_mode = {
 		.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
@@ -147,8 +157,9 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
 
 	/* Enable CS */
 	out = nrf_vpr_csr_vio_out_get();
-	out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
-	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
+	out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+			       : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
 	nrf_vpr_csr_vio_out_set(out);
 
 	/* Start counter */
@@ -170,9 +181,11 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
 	/* Deselect slave */
 	if (!hold_ce) {
 		out = nrf_vpr_csr_vio_out_get();
-		out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
-		out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
-		out |= PIN_OUT_LOW_MASK(SCLK_PIN);
+		out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+			 PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+		out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+				       : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+		out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
 		nrf_vpr_csr_vio_out_set(out);
 	}
 

diff --git a/applications/sdp/mspi/src/hrt/hrt.h b/applications/sdp/mspi/src/hrt/hrt.h
@@ -10,13 +10,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#define SCLK_PIN 0
-#define D0_PIN	 1
-#define D1_PIN	 2
-#define D2_PIN	 3
-#define D3_PIN	 4
-#define CS_PIN	 5
-
 /* Max word size. */
 #define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX