SDP MSPI driver

CODEOWNERS

@@ -283,6 +283,7 @@
 /drivers/gpio/                            @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
 /drivers/hw_cc3xx/                        @nrfconnect/ncs-co-drivers @nrfconnect/ncs-aegir
 /drivers/mpsl/                            @nrfconnect/ncs-co-drivers @nrfconnect/ncs-dragoon
+/drivers/mspi/                            @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
 /drivers/net/                             @nrfconnect/ncs-co-drivers @doki-nordic
 /drivers/serial/                          @nrfconnect/ncs-co-drivers @nordic-krch
 /drivers/sensor/bh1749/                   @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
@@ -317,6 +318,7 @@
 /include/drivers/flash/                   @nrfconnect/ncs-co-drivers
 /include/drivers/gpio/                    @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
 /include/drivers/bme68x_iaq.h             @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
+/include/drivers/mspi/nrfe_mspi.h         @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
 /include/drivers/sensor_sim.h             @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
 /include/drivers/sensor_stub.h            @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
 /include/emds/                            @balaklaka @nrfconnect/ncs-paladin
@@ -608,6 +610,7 @@
 /scripts/print_docker_image.sh            @nrfconnect/ncs-ci
 /scripts/print_toolchain_checksum.sh      @nrfconnect/ncs-ci
 /scripts/sdp/                             @nrfconnect/ncs-ll-ursus
+/scripts/twister/alt/zephyr/tests/drivers/mspi/api/testcase.yaml @nrfconnect/ncs-ll-ursus
 
 /scripts/docker/*.rst                     @nrfconnect/ncs-doc-leads
 /scripts/hid_configurator/*.rst           @nrfconnect/ncs-si-bluebagel-doc

applications/sdp/mspi/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(sdp_mspi)
+
+sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
+
+target_sources(app PRIVATE src/main.c)
+target_sources(app PRIVATE src/hrt/hrt.s)
+
+add_dependencies(app asm_check)

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,46 @@
+# Single-threaded
+CONFIG_MULTITHREADING=n
+CONFIG_KERNEL_MEM_POOL=n
+CONFIG_LOG=n
+
+# Drivers and peripherals
+CONFIG_I2C=n
+CONFIG_WATCHDOG=n
+CONFIG_GPIO=n
+CONFIG_PINCTRL=n
+CONFIG_SPI=n
+CONFIG_SERIAL=n
+CONFIG_FLASH=n
+
+# Power management
+CONFIG_PM=n
+
+# Interrupts
+CONFIG_DYNAMIC_INTERRUPTS=n
+CONFIG_IRQ_OFFLOAD=n
+CONFIG_GEN_SW_ISR_TABLE=n
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+CONFIG_FPU=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
+
+# Console
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_STDOUT_CONSOLE=n
+CONFIG_PRINTK=n
+CONFIG_EARLY_CONSOLE=n
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
+
+# No timer support in the kernel
+CONFIG_SYS_CLOCK_EXISTS=n
+
+CONFIG_OUTPUT_DISASSEMBLY=y
+CONFIG_COMMON_LIBC_MALLOC=n

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@2003c000 {
+				reg = <0x2003c000 0x0800>;
+			};
+
+			sram_rx: memory@2003c800 {
+				reg = <0x2003c800 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_rram {
+	reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_sram {
+	reg = <0x2003d000 DT_SIZE_K(12)>;
+	ranges = <0x0 0x2003d000 0x3000>;
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+	interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
+	nordic,tasks = <1>;
+	nordic,tasks-mask = <0x00010000>;
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&gpiote20 {
+	status = "disabled";
+};
+
+&gpiote30 {
+	status = "disabled";
+};
+
+&grtc {
+	status = "disabled";
+};
+
+&uart20 {
+	status = "disabled";
+};
+
+&uart30 {
+	status = "disabled";
+};
+
+&pwm20 {
+	status = "disabled";
+};

applications/sdp/mspi/prj.conf

@@ -0,0 +1,3 @@
+CONFIG_MBOX=y
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

applications/sdp/mspi/sample.yaml

@@ -0,0 +1,14 @@
+sample:
+  name: SDP mSPI application
+  description: SDP mSPI application
+common:
+  integration_platforms:
+    - nrf54l15dk/nrf54l15/cpuflpr
+tests:
+  applications.sdp.mspi:
+    build_only: true
+    sysbuild: true
+    platform_allow: nrf54l15dk/nrf54l15/cpuflpr
+    tags: ci_build sysbuild mspi
+    required_snippets:
+      - sdp-mspi

applications/sdp/mspi/src/hrt/hrt.c

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+#include "hrt.h"
+#include <hal/nrf_vpr_csr_vio.h>
+#include <hal/nrf_vpr_csr_vtim.h>
+
+#define CLK_FIRST_CYCLE_MULTIPLICATOR (3)
+
+void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
+			  uint8_t word_size, bool ce_enable_state, bool hold_ce)
+{
+
+	NRFX_ASSERT(word_size <= MAX_WORD_SIZE);
+	/* Configuration step */
+	uint16_t dir = nrf_vpr_csr_vio_dir_get();
+
+	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+
+	uint16_t out = nrf_vpr_csr_vio_out_get();
+
+	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+
+	nrf_vpr_csr_vio_mode_out_t out_mode = {
+		.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
+		.frame_width = 1,
+	};
+
+	nrf_vpr_csr_vio_mode_out_set(&out_mode);
+	nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
+
+	nrf_vpr_csr_vio_config_t config;
+
+	nrf_vpr_csr_vio_config_get(&config);
+	config.input_sel = false;
+	nrf_vpr_csr_vio_config_set(&config);
+
+	/* Fix position of data if word size < MAX_WORD_SIZE,
+	 * so that leading zeros would not be printed instead of data bits.
+	 */
+	if (word_size < MAX_WORD_SIZE) {
+		for (uint8_t i = 0; i < data_len; i++) {
+			data[i] = data[i] << (MAX_WORD_SIZE - word_size);
+		}
+	}
+
+	/* Counter settings */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
+	nrf_vpr_csr_vtim_simple_counter_top_set(0, counter_top);
+
+	/* Set number of shifts before OUTB needs to be updated.
+	 * First shift needs to be increased by 1.
+	 */
+	nrf_vpr_csr_vio_shift_cnt_out_set(word_size);
+	nrf_vpr_csr_vio_shift_cnt_out_buffered_set(word_size - 1);
+
+	/* Enable CS */
+	out = nrf_vpr_csr_vio_out_get();
+	out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+			       : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	nrf_vpr_csr_vio_out_set(out);
+
+	/* Start counter */
+	nrf_vpr_csr_vtim_simple_counter_set(0, CLK_FIRST_CYCLE_MULTIPLICATOR * counter_top);
+
+	/* Send data */
+	for (uint8_t i = 0; i < data_len; i++) {
+		nrf_vpr_csr_vio_out_buffered_reversed_byte_set(data[i]);
+	}
+
+	/* Clear all bits, wait until the last word is sent */
+	nrf_vpr_csr_vio_out_buffered_set(0);
+
+	/* Final configuration */
+	out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE;
+	nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode);
+	nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
+
+	/* Deselect slave */
+	if (!hold_ce) {
+		out = nrf_vpr_csr_vio_out_get();
+		out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+			 PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+		out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+				       : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+		out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
+		nrf_vpr_csr_vio_out_set(out);
+	}
+
+	/* Stop counter */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
+}
+
+void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
+			uint8_t word_size, bool ce_enable_state, bool hold_ce)
+{
+	NRFX_ASSERT(word_size % 4 == 0);
+	NRFX_ASSERT(word_size <= MAX_WORD_SIZE);
+	/* Configuration step */
+	uint16_t dir = nrf_vpr_csr_vio_dir_get();
+
+	nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+
+	uint16_t out = nrf_vpr_csr_vio_out_get();
+
+	nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
+				PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+				PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+
+	nrf_vpr_csr_vio_mode_out_t out_mode = {
+		.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
+		.frame_width = 4,
+	};
+
+	nrf_vpr_csr_vio_mode_out_set(&out_mode);
+	nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
+
+	nrf_vpr_csr_vio_config_t config;
+
+	nrf_vpr_csr_vio_config_get(&config);
+	config.input_sel = false;
+	nrf_vpr_csr_vio_config_set(&config);
+
+	/* Fix position of data if word size < MAX_WORD_SIZE,
+	 * so that leading zeros would not be printed instead of data.
+	 */
+	if (word_size < MAX_WORD_SIZE) {
+		for (uint8_t i = 0; i < data_len; i++) {
+			data[i] = data[i] << (MAX_WORD_SIZE - word_size);
+		}
+	}
+
+	/* Counter settings */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
+	nrf_vpr_csr_vtim_simple_counter_top_set(0, counter_top);
+
+	/* Set number of shifts before OUTB needs to be updated.
+	 * First shift needs to be increased by 1.
+	 */
+	nrf_vpr_csr_vio_shift_cnt_out_set(word_size / 4);
+	nrf_vpr_csr_vio_shift_cnt_out_buffered_set(word_size / 4 - 1);
+
+	/* Enable CS */
+	out = nrf_vpr_csr_vio_out_get();
+	out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+			       : PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+	nrf_vpr_csr_vio_out_set(out);
+
+	/* Start counter */
+	nrf_vpr_csr_vtim_simple_counter_set(0, 3 * counter_top);
+
+	/* Send data */
+	for (uint8_t i = 0; i < data_len; i++) {
+		nrf_vpr_csr_vio_out_buffered_reversed_byte_set(data[i]);
+	}
+
+	/* Clear all bits, wait until the last word is sent */
+	nrf_vpr_csr_vio_out_buffered_set(0);
+
+	/* Final configuration */
+	out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE;
+	nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode);
+	nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
+
+	/* Deselect slave */
+	if (!hold_ce) {
+		out = nrf_vpr_csr_vio_out_get();
+		out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
+			 PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
+		out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
+				       : PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
+		out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
+		nrf_vpr_csr_vio_out_set(out);
+	}
+
+	/* Stop counter */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
+}