[nrf noup] boards: Add non secure target for nrf54L15dk

This adds the `nrf54l15dk/nrf54l15/cpuapp/ns` board target.

Signed-off-by: Georgios Vasilakis <[email protected]>
Signed-off-by: Tomi Fontanilles <[email protected]>

boards/nordic/nrf54l15dk/Kconfig

@@ -0,0 +1,34 @@
+# nRF54L15 DK board configuration
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+
+config NRF_MPC_REGION_SIZE
+	hex
+	default 0x1000
+	help
+	  Region size for the Memory Protection Controller (MPC) in bytes.
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default NRF_MPC_REGION_SIZE
+	help
+	  This defines the flash region size from the TRUSTZONE perspective.
+	  It is used when configuring the TRUSTZONE and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TRUSTZONE without depending
+	  on peripheral specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default NRF_MPC_REGION_SIZE
+	help
+	  This defines the RAM region size from the TRUSTZONE perspective.
+	  It is used when configuring the TRUSTZONE and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TRUSTZONE without depending
+	  on peripheral specific symbols.
+
+endif #BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS

boards/nordic/nrf54l15dk/Kconfig.defconfig

@@ -11,3 +11,18 @@ config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
 endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP
+
+if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+	default y
+	depends on BUILD_WITH_TFM
+
+endif #BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS

boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk

@@ -2,6 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF54L15DK
-	select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP
+	select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
 	select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
 					    BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

boards/nordic/nrf54l15dk/board.cmake

@@ -7,5 +7,13 @@ elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
   board_runner_args(jlink "--speed=4000")
 endif()
 
+if(BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54l15dk/board.yml

@@ -6,3 +6,5 @@ board:
     variants:
     - name: xip
       cpucluster: cpuflpr
+    - name: ns
+      cpucluster: cpuapp

boards/nordic/nrf54l15dk/doc/index.rst

@@ -98,7 +98,7 @@ to be build as multicore configuration with code snippet called ``vpr_launcher``
 for the application core.
 
 Enter the following command to compile ``hello_world`` for the FLPR core::
- west build -p -b nrf54l15pdk/nrf54l15/cpuflpr --sysbuild -- -DSB_VPR_LAUNCHER=y
+ west build -p -b nrf54l15dk/nrf54l15/cpuflpr --sysbuild -- -DSB_VPR_LAUNCHER=y
 
 Flashing
 ========

boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include "nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp";
+	model = "Nordic nRF54L15 DK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};

boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml

@@ -0,0 +1,22 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+identifier: nrf54l15dk/nrf54l15/cpuapp/ns
+name: nRF54l15-DK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s

boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y