Supports XCVMEM extension instructions.

[pz9115]

Supports XCVMEM extension instructions on QEMU 9.0 version, please update the dev branch first,

commit see pz9115@265859e

[pz9115]

Here we can have a simple c program to verify the QEMU changes, since the logical is same, just verify cv.lb/cv.sb instructions in this case.

Firstly, we set the cvls.c to generate normal lb/sb instructions

#include <stdio.h>
#include <stdint.h>

int foo(int8_t a,int b){
   return a+b;
}

int main() {

    int res = foo(170,85);

    printf("%x\n", res);
    return 0;
}

Compile with corev-gcc ( use -S), we got the assemble code cvls.s

	.file	"cvls.c"
	.option nopic
	.attribute arch, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xcvmem1p0"
	.attribute unaligned_access, 0
	.attribute stack_align, 16
	.text
	.align	1
	.globl	foo
	.type	foo, @function
foo:
	addi	sp,sp,-32
	sw	ra,28(sp)
	sw	s0,24(sp)
	addi	s0,sp,32
	mv	a5,a0
	sw	a1,-24(s0)
	sb	a5,-17(s0)
	lb	a4,-17(s0)
	lw	a5,-24(s0)
	add	a5,a4,a5
	mv	a0,a5
	lw	ra,28(sp)
	lw	s0,24(sp)
	addi	sp,sp,32
	jr	ra
	.size	foo, .-foo
	.section	.rodata
	.align	2
.LC0:
	.string	"%x\n"
	.text
	.align	1
	.globl	main
	.type	main, @function
main:
	addi	sp,sp,-32
	sw	ra,28(sp)
	sw	s0,24(sp)
	addi	s0,sp,32
	li	a1,85
	li	a0,-86
	call	foo
	sw	a0,-20(s0)
	lw	a1,-20(s0)
	lui	a5,%hi(.LC0)
	addi	a0,a5,%lo(.LC0)
	call	printf
	li	a5,0
	mv	a0,a5
	lw	ra,28(sp)
	lw	s0,24(sp)
	addi	sp,sp,32
	jr	ra
	.size	main, .-main
	.ident	"GCC: (gd3150e4de84) 14.1.0"
	.section	.note.GNU-stack,"",@progbits

then we need to modify the sb/lb into cv.sb/cv.lb in function foo, here is an example

foo:
        addi    sp, sp, -32
        sw      ra, 28(sp)
        sw      s0, 24(sp)
        addi    s0, sp, 32
        mv      a5, a0
        sw      a1, -24(s0)
        addi    t0, s0, -17     // store the address into t0
        cv.sb   a5, (t0), 0     // use cv.sb to store then t0 += Sext(0)
        cv.lb   a4, (t0), 0     //  use cv.lb to load then t0 += Sext(0)
        lw      a5, -24(s0)
        add     a5, a4, a5
        mv      a0, a5
        lw      ra, 28(sp)
        lw      s0, 24(sp)
        addi    sp, sp, 32
        jr      ra

Use corev-gcc to generate two elf files with different source assemble codes, the modified assemble codes need assign -march with xcvmem extension.

Finally, use qemu to run both elf file, see if we can get the same result.

To verify the post-increment feature, we can adjust the third argument in cv.sb, here is an example

foo:
        addi    sp, sp, -32
        sw      ra, 28(sp)
        sw      s0, 24(sp)
        addi    s0, sp, 32
        mv      a5, a0
        sw      a1, -24(s0)
        addi    t0, s0, -17     // store the address into t0
        cv.sb   a5, (t0), 20     // use cv.sb to store then t0 += Sext(20)
        addi    t0, t0, -20      // subtract the addition 20
        cv.lb   a4, (t0), -24     //  use cv.lb to load then t0 += Sext(0)
        lw      a5, t0(s0)
        add     a5, a4, a5
        mv      a0, a5
        lw      ra, 28(sp)
        lw      s0, 24(sp)
        addi    sp, sp, 32
        jr      ra

[pz9115]

This based on QEMU version for 9.0.1 release, need to checkout the branch.

commit 60b4f3a (tag: v9.0.1)