Os fixes6

[mohammadshahidzade]

This PR includes initial changes that will be necessary to run an operating system on multicore CVA5.
In addition to clarity and QoL changes, this primarily includes:

• Full support for the 20240411 RISC-V privileged architecture (previously a draft spec from ~2017-2019 was mostly supported)
• New separate TLB's for instructions and data
• Support for Sv32 virtual memory
• Many significant bugfixes for interrupt and exception handling (can close Interrupts can lead to MEPC inconsistent with register state / actually retired operations or pointing to entirely illegal instructions #19)
• Support for the RISC-V atomic extension (can close State of AMO support #21)
• Simulation support for the latest version of Verilator
• Multicore support with cache snooping, validated with configurations of 1, 2, and 4 cores.
• Optimized PLIC and CLINT implementation required for full multicore Linux support.
• Backward compatibility verified with both the LiteX framework and Vivado block design, ensuring seamless operation across both environments.
• Validated on multiple FPGA boards, including the VCU118 and Digilent Nexys.
• Performance: Achieves up to 250 MHz on the VCU118 for a single core.
• Software compatibility tested with Linux 5.18.0 and OpenSBI v0.8-2-ga9ce3ad.
• Ability to configure it back to the original bare-metal system by only changing the CPU configurations.