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flash/stm32l4x: support STM32WBA5xx devices
STM32WBA5x have a single bank flash up to 1MB Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b Signed-off-by: Tarek BOCHKATI <[email protected]> Signed-off-by: Erwan Gouriou <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/7694 Tested-by: jenkins Reviewed-by: Tomas Vanek <[email protected]> Reviewed-by: Antonio Borneo <[email protected]>
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# SPDX-License-Identifier: GPL-2.0-or-later | ||
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# script for stm32wbax family | ||
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# | ||
# stm32wba devices support both JTAG and SWD transports. | ||
# | ||
source [find target/swj-dp.tcl] | ||
source [find mem_helper.tcl] | ||
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if { [info exists CHIPNAME] } { | ||
set _CHIPNAME $CHIPNAME | ||
} else { | ||
set _CHIPNAME stm32wbax | ||
} | ||
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# Work-area is a space in RAM used for flash programming | ||
# By default use 64kB | ||
if { [info exists WORKAREASIZE] } { | ||
set _WORKAREASIZE $WORKAREASIZE | ||
} else { | ||
set _WORKAREASIZE 0x10000 | ||
} | ||
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#jtag scan chain | ||
if { [info exists CPUTAPID] } { | ||
set _CPUTAPID $CPUTAPID | ||
} else { | ||
if { [using_jtag] } { | ||
set _CPUTAPID 0x6ba00477 | ||
} else { | ||
# SWD IDCODE (single drop, arm) | ||
set _CPUTAPID 0x6ba02477 | ||
} | ||
} | ||
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | ||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | ||
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if {[using_jtag]} { | ||
jtag newtap $_CHIPNAME bs -irlen 5 | ||
} | ||
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set _TARGETNAME $_CHIPNAME.cpu | ||
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 | ||
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | ||
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME | ||
flash bank $_CHIPNAME.otp stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME | ||
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# Common knowledges tells JTAG speed should be <= F_CPU/6. | ||
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on | ||
# the safe side. | ||
# | ||
# Note that there is a pretty wide band where things are | ||
# more or less stable, see http://openocd.zylin.com/#/c/3366/ | ||
adapter speed 500 | ||
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adapter srst delay 100 | ||
if {[using_jtag]} { | ||
jtag_ntrst_delay 100 | ||
} | ||
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reset_config srst_nogate | ||
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if {![using_hla]} { | ||
# if srst is not fitted use SYSRESETREQ to | ||
# perform a soft reset | ||
cortex_m reset_config sysresetreq | ||
} | ||
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$_TARGETNAME configure -event reset-init { | ||
# CPU comes out of reset with HSION | HSIRDY. | ||
# Use HSI 16 MHz clock, compliant even with VOS == 2. | ||
# 1 WS compliant with VOS == 2 and 16 MHz. | ||
mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1 | ||
mmw 0x56020C00 0x00000100 0x00000000 ;# RCC_CR |= HSION | ||
mmw 0x56020C1C 0x00000000 0x00000002 ;# RCC_CFGR1: SW=HSI16 | ||
# Boost JTAG frequency | ||
adapter speed 4000 | ||
} | ||
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$_TARGETNAME configure -event reset-start { | ||
# Reset clock is HSI (16 MHz) | ||
adapter speed 2000 | ||
} | ||
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$_TARGETNAME configure -event examine-end { | ||
# Enable debug during low power modes (uses more power) | ||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | ||
mmw 0xE0042004 0x00000006 0 | ||
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# Stop watchdog counters during halt | ||
# DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP | ||
mmw 0xE0042008 0x00001800 0 | ||
} | ||
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 | ||
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu | ||
proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { | ||
targets $_targetname | ||
} | ||
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" |