contrib/firmware: Add direction control for 'SCL' i2c signal

We want to keep the tri-state buffers located between the FPGA
and the board, in 'Z' state until we launch an i2c connection.

We launch an i2c start condition, make the SCL
direction 'OUT' to start the i2c protocol and at the end
of the i2c connection at the stop condition, we re-make
the tri-state buffers at 'Z' state.

Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64
Signed-off-by: Ahmed BOUDJELIDA <[email protected]>
Reviewed-on: https://review.openocd.org/c/openocd/+/7989
Tested-by: jenkins
Reviewed-by: Antonio Borneo <[email protected]>

contrib/firmware/angie/c/include/io.h

@@ -66,7 +66,7 @@
 #define PIN_SDA         IOD0
 #define PIN_SCL         IOD1
 #define PIN_SDA_DIR     IOD2
-/* PD3 Not Connected */
+#define PIN_SCL_DIR     IOD3
 /* PD4 Not Connected */
 /* PD5 Not Connected */
 /* PD6 Not Connected */

contrib/firmware/angie/c/src/i2c.c

@@ -14,6 +14,9 @@
 
 void start_cd(void)
 {
+	PIN_SCL_DIR = 0;
+	PIN_SDA_DIR = 0;
+	delay_us(10);
 	PIN_SDA = 0; //SDA = 1;
 	delay_us(1);
 	PIN_SCL = 0; //SCL = 1;
@@ -40,6 +43,10 @@ void stop_cd(void)
 	delay_us(1);
 	PIN_SDA = 1;
 	delay_us(1);
+	PIN_SDA_DIR = 1;
+	delay_us(1);
+	PIN_SCL_DIR = 1;
+	delay_us(1);
 }
 
 void clock_cd(void)

contrib/firmware/angie/c/src/usb.c

@@ -886,9 +886,6 @@ void io_init(void)
 	PORTACFG = 0x01;	/* 0: normal ou 1: alternate function (each bit) */
 	OEA = 0xEF;	/* all OUT exept INIT_B IN */
 	IOA = 0xFF;
-	PIN_RDWR_B = 1;
-	PIN_CSI_B = 1;
-	PIN_PROGRAM_B = 1;
 
 	/* PORT B */
 	OEB = 0xEF;	/* all OUT exept TDO */
@@ -899,8 +896,6 @@ void io_init(void)
 	PIN_TDI = 0;
 	PIN_SRST = 1;
 
-
-
 	/* PORT C */
 	PORTCCFG = 0x00;	/* 0: normal ou 1: alternate function (each bit) */
 	OEC = 0xFF;
@@ -909,5 +904,4 @@ void io_init(void)
 	/* PORT D */
 	OED = 0xFF;
 	IOD = 0xFF;
-	PIN_SDA_DIR = 0;
 }

contrib/firmware/angie/hdl/src/angie_bitstream.ucf

@@ -20,6 +20,7 @@ net SRST    LOC = 'P61' ;
 net SDA		LOC = 'P50' ;
 net SCL     LOC = 'P51' ;
 net SDA_DIR	LOC = 'P56' ;
+net SCL_DIR	LOC = 'P57' ;
 
 net SI_TDO	LOC = 'P16' ;
 net SO_TRST	LOC = 'P32' ;

contrib/firmware/angie/hdl/src/angie_bitstream.vhd

@@ -26,8 +26,9 @@ entity S609 is port(
   SDA : inout std_logic;
   SDA_DIR : in std_logic;
   SCL : in std_logic;
+  SCL_DIR : in std_logic;
 
-  FTP : out std_logic_vector(7 downto 0):=(others => '1'); -- Test points
+  FTP : out std_logic_vector(7 downto 0); -- Test points
   SI_TDO : in  std_logic;
   ST_0 : out std_logic;
   ST_1 : out std_logic;
@@ -55,8 +56,6 @@ begin
 ST_0 <= '0';
 ST_1 <= '1';
 
-ST_4 <= '0';
-
 --TDO:
 TDO <= not SI_TDO;
 
@@ -75,13 +74,21 @@ SO_SDA_OUT <= SDA;
 
 process(SDA_DIR)
 begin
-	if(SDA_DIR = '1') then
-		ST_5 <= '1';
-	else
+	if(SDA_DIR = '0') then
 		ST_5 <= '0';
+	else
+		ST_5 <= '1';
 	end if;
 end process;
 
+process(SCL_DIR)
+begin
+	if(SCL_DIR = '0') then
+		ST_4 <= '0';
+	else
+		ST_4 <= '1';
+	end if;
+end process;
 
 --Points de test:
 FTP(0) <= SDA;