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target/arm_adi_v5: fix DP SELECT logic
The original code supported ADIv5 only, just one SELECT register with some reserved bits - the pseudo value DP_SELECT_INVALID was just fine to indicate the DP SELECT register is in an unknown state. Added ADIv6 support required DP SELECT and SELECT1 registers without reserved bits. Therefore DP_SELECT_INVALID value became reachable as a (fortunately not really used) ADIv6 AP ADDR. JTAG DPBANKSEL setting support introduced with ADIv6 does not honor DP_SELECT_INVALID correctly: required select value gets compared to DP_SELECT_INVALID value and the most common zero bank does not trigger DP SELECT write. DP banked registers need just to set DP SELECT. ADIv6 AP register addressing scheme may use both DP SELECT and SELECT1. This further complicates using a single invalid value. Moreover the difference how the SWD line reset influences DPBANKSEL field between ADIv5 and ADIv6 deserves better handling than setting select cache to zero and then to DP_SELECT_INVALID in a very specific code positions. Introduce bool flags indicating the validity of each SELECT register and one SWD specific for DPBANKSEL field. Use the latter to prevent selecting DP BANK before taking the connection out of reset by reading DPIDR. Treat DP SELECT and SELECT1 individually in ADIv6 64-bit mode. Update comments to reflect the difference between ADIv5 and ADIv6 in SWD line reset. Change-Id: Ibbb0b06cb592be072571218b666566a13d8dff0e Signed-off-by: Tomas Vanek <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/7541 Tested-by: jenkins Reviewed-by: Antonio Borneo <[email protected]>
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