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Add RISC-V 64 Support for LuaJIT v2.1 #236

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34a74ff
riscv(support): add RISC-V 64 arch base definition
infiWang Mar 5, 2024
155917e
riscv(dynasm): add RISC-V support
infiWang Mar 5, 2024
3f2a9a2
riscv(interp): add register definition
infiWang Mar 5, 2024
ac5e7a8
riscv(interp): add frame definition
infiWang Mar 5, 2024
8a1761f
riscv(interp): add helper macros and typedefs
infiWang Mar 5, 2024
7dcaa4d
riscv(interp): add base assembly interpreter VM
infiWang Mar 6, 2024
eb87e6f
riscv(support): add target definition
infiWang Mar 6, 2024
ad11ee8
riscv(ffi): add call convention and support framework
infiWang Mar 6, 2024
e36801c
riscv(support): add extension detection
infiWang Mar 6, 2024
686ebf5
riscv(jit): add insn emitter
infiWang Mar 6, 2024
6cd6f3f
riscv(jit): add IR assembler
infiWang Mar 6, 2024
d8c992d
riscv(interp): add VM builder support
infiWang Mar 6, 2024
7a0691d
riscv(misc): add bytecode listing support
infiWang Mar 6, 2024
6f1f257
riscv(jit): add hooks in interpreter
infiWang Mar 6, 2024
ab2db4b
riscv(interp): add DWARF info
infiWang Mar 6, 2024
2e8e5ab
riscv(jit): add GDBJIT support
infiWang Mar 6, 2024
012b47e
riscv(support,linux): add Linux specfic icache sync codepath
infiWang Mar 6, 2024
2b0c38c
riscv(support,linux): make mremap() non-moving due to VA space woes
infiWang Mar 6, 2024
e425d91
riscv(misc): add disassmbler support
infiWang Mar 6, 2024
52af6d8
riscv(misc): add support in Makefile
infiWang Mar 6, 2024
9615a22
riscv(support,linux): use HWPROBE for ISE detection
infiWang Aug 21, 2024
ea214b2
riscv(interp): strip excessive extended branch (^B+J)
infiWang Jan 15, 2025
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riscv(interp): add VM builder support
  • Loading branch information
infiWang committed Jan 23, 2025
commit d8c992d888137be24076a392860f963f678e96c3
2 changes: 2 additions & 0 deletions src/host/buildvm.c
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,8 @@ static int collect_reloc(BuildCtx *ctx, uint8_t *addr, int idx, int type);
#include "../dynasm/dasm_mips.h"
#elif LJ_TARGET_S390X
#include "../dynasm/dasm_s390x.h"
#elif LJ_TARGET_RISCV64
#include "../dynasm/dasm_riscv.h"
#else
#error "No support for this architecture (yet)"
#endif
Expand Down
31 changes: 31 additions & 0 deletions src/host/buildvm_asm.c
Original file line number Diff line number Diff line change
Expand Up @@ -208,6 +208,34 @@ static void emit_asm_wordreloc(BuildCtx *ctx, uint8_t *p, int n,
"Error: unsupported opcode %08x for %s symbol relocation.\n",
ins, sym);
exit(1);
#elif LJ_TARGET_RISCV64
if ((ins & 0x7f) == 0x17u) {
fprintf(ctx->fp, "\tauipc x%d, %s\n", (ins >> 7) & 31, sym);
} else if ((ins & 0x7f) == 0x67u) {
fprintf(ctx->fp, "\tjalr x%d, x%d, %s\n", (ins >> 7) & 31, (ins >> 15) & 31, sym);
} else if ((ins & 0x7f) == 0x6fu) {
fprintf(ctx->fp, "\tjal x%d, %s\n", (ins >> 7) & 31, sym);
} else if ((ins & 0x7f) == 0x03u) {
uint8_t funct3 = (ins >> 12) & 7;
uint8_t rd = (ins >> 7) & 31, rs1 = (ins >> 15) & 31;
switch (funct3) {
case 0: fprintf(ctx->fp, "\tlb"); break;
case 1: fprintf(ctx->fp, "\tlh"); break;
case 2: fprintf(ctx->fp, "\tlw"); break;
case 3: fprintf(ctx->fp, "\tld"); break;
case 4: fprintf(ctx->fp, "\tlbu"); break;
case 5: fprintf(ctx->fp, "\tlhu"); break;
case 6: fprintf(ctx->fp, "\tlwu"); break;
default: goto rv_reloc_err;
}
fprintf(ctx->fp, " x%d, %s(x%d)\n", rd, sym, rs1);
} else {
rv_reloc_err:
fprintf(stderr,
"Error: unsupported opcode %08x for %s symbol relocation.\n",
ins, sym);
exit(1);
}
#else
#error "missing relocation support for this architecture"
#endif
Expand Down Expand Up @@ -303,6 +331,9 @@ void emit_asm(BuildCtx *ctx)
#endif
#if LJ_TARGET_MIPS
fprintf(ctx->fp, "\t.set nomips16\n\t.abicalls\n\t.set noreorder\n\t.set nomacro\n");
#endif
#if LJ_TARGET_RISCV64
fprintf(ctx->fp, ".option arch, -c\n.option norelax\n");
#endif
emit_asm_align(ctx, 4);

Expand Down