Addition of gdb init for 117x

Co-authored-by: iannxp <[email protected]>
Signed-off-by: Peter van der Perk <[email protected]>

Support/gdbtrace.init

@@ -85,6 +85,7 @@ set $CPU_NRF=3
 set $CPU_EFR32=4
 set $CPU_TM4C=5
 set $CPU_S32K344=6
+set $CPU_IMXRT117X=7
 
 # ====================================================================
 set $CDBBASE=0xE000EDF0
@@ -103,6 +104,17 @@ define _setAddressesIMXRT
 # Locations in the memory map for interesting things on IMXRT
 end
 
+define _setAddressesIMXRT117X
+  # Locations in the memory map for interesting things on IMXRT117X.
+  set $TPIU_TRACE_BASE    = 0xe0046000
+  set $TPIU_SWO_BASE      = 0xe0048000
+  set $FUNNEL_CSSYS_BASE  = 0xe0045000
+  set $FUNNEL_M7_BASE     = 0xe0043000
+
+  # Indicate use of IMXRT117X as the target.
+  set $CPU = $CPU_IMXRT117X
+end
+
 define _setAddressesNRF
 # Locations in the memory map for interesting things on NRF
 end
@@ -801,6 +813,34 @@ enableIMXRT1021SWO Configure output pin on IMXRT1060 for SWO use.
 end
 # ====================================================================
 
+define enableIMXRT117XSWO
+  #set language c
+  _setAddressesIMXRT117X
+
+  # Configure trace funnels/ATB.
+  set *($FUNNEL_CSSYS_BASE + 0xfb0) = 0xc5acce55
+  set *($FUNNEL_CSSYS_BASE) |= 0xff
+
+  set *($FUNNEL_M7_BASE + 0xfb0) = 0xc5acce55
+  set *($FUNNEL_M7_BASE) |= 0xff
+
+  # TODO: configure trace subsystem clocks.
+
+  # Configure GPIO_LPSR_11 mux and pad for SWO.
+  set *(0x40c0802c) = 0x7
+  set *(0x40c0806c) = 0x2
+
+  # Allow access to SWO TPIU registers.
+  set *($TPIU_SWO_BASE + 0xfb0) = 0xc5acce55
+
+  # Set $TPIUBASE for use by other commands in this file.
+  set $TPIUBASE = $TPIU_SWO_BASE
+
+  #set language auto
+end
+
+# ====================================================================
+
 define enableSTM32SWO
   #set language c