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Fixes in traceDecoder and loadelf #159

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merged 7 commits into from
Oct 27, 2024
Merged

Fixes in traceDecoder and loadelf #159

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a53c22e
traceDecoder_etm4 bug fixes
Oct 24, 2024
3c326d2
TraceDecoder
Oct 24, 2024
29c8a18
loadelf fix
Oct 24, 2024
f0abfb8
update
Oct 24, 2024
5f04cb4
loadelf fix
Oct 24, 2024
e4c0320
Merge remote-tracking branch 'origin/PR' into PR
Oct 24, 2024
ff18fc2
_processFunctionDie fix
Oct 24, 2024
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3 changes: 3 additions & 0 deletions Inc/traceDecoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,9 @@ struct TRACECPUState

// Convinience, for debug reporting
genericsReportCB report;

// Debugging
uint64_t overflows;
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While using instruction tracing we had problems with overflows even with implicit tracing. Because there is no feedback I added an overflow counter and a debug message.

};

// ============================================================================
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26 changes: 17 additions & 9 deletions Src/loadelf.c
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Expand Up @@ -369,15 +369,15 @@ static void _processFunctionDie( struct symbol *p, Dwarf_Debug dbg, Dwarf_Die di
attr_tag = DW_AT_abstract_origin;
dwarf_attr( die, attr_tag, &attr_data, 0 );
dwarf_global_formref( attr_data, &abstract_origin_offset, 0 );
dwarf_offdie_b( dbg, abstract_origin_offset, IS_INFO, &abstract_origin_die, 0 );
isinline = true;
}
else
{
dwarf_highpc_b ( die, &h, 0, &formclass, 0 );
dwarf_lowpc ( die, &l, 0 );
if (DW_DLV_OK == dwarf_offdie_b( dbg, abstract_origin_offset, IS_INFO, &abstract_origin_die, 0 ))
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There has been an issue with inline low/high addresses, where function names could not be matched to addresses this should be fixed with this part.

{
isinline = true;
}
}

dwarf_highpc_b ( die, &h, 0, &formclass, 0 );
dwarf_lowpc ( die, &l, 0 );

if ( formclass == DW_FORM_CLASS_CONSTANT )
{
h += l;
Expand Down Expand Up @@ -1001,7 +1001,7 @@ char *symbolDisassembleLine( struct symbol *p, enum instructionClass *ic, symbol
if ( !p->caphandle )
{
/* Disassembler isn't initialised yet */
if ( cs_open( CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_LITTLE_ENDIAN, &p->caphandle ) != CS_ERR_OK )
if ( cs_open( CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_LITTLE_ENDIAN + CS_MODE_MCLASS, &p->caphandle ) != CS_ERR_OK )
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Some Instructions could not be decoded because this Makro was missing.

{
return NULL;
}
Expand Down Expand Up @@ -1044,6 +1044,14 @@ char *symbolDisassembleLine( struct symbol *p, enum instructionClass *ic, symbol
&& strstr( insn->op_str, "pc" ) )
) ? LE_IC_JUMP : 0;

/* create a copy to check if load in pc */
char *copy = strdup(insn->op_str);
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@lvb2000 lvb2000 Oct 24, 2024 •
edited
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Load to PC were not detected as Jump instructions.

*ic |= (
( ( ( insn->id == ARM_INS_LDR ) )
&& strstr(strtok(copy,","), "pc" ) )
) ? LE_IC_JUMP : 0;
free(copy);

/* Was it an exception return? */
*ic |= ( ( insn->id == ARM_INS_ERET ) ) ? LE_IC_JUMP | LE_IC_IRET : 0;

Expand Down Expand Up @@ -1072,7 +1080,7 @@ char *symbolDisassembleLine( struct symbol *p, enum instructionClass *ic, symbol

if ( newaddr )
{
*newaddr = detail->arm.operands[0].imm;
*newaddr = detail->arm.operands[n].imm;
}

break;
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11 changes: 9 additions & 2 deletions Src/traceDecoder_etm4.c
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Expand Up @@ -185,6 +185,11 @@ static bool _pumpAction( struct TRACEDecoderEngine *e, struct TRACECPUState *cpu
}
else
{
if( c == 0x05 && j->asyncCount == 1)
{
cpu->overflows++;
DEBUG( "Overflow Detected. ReSync Trace Stream:" EOL );
}
j->asyncCount = c ? 0 : j->asyncCount + 1;

switch ( j->p )
Expand Down Expand Up @@ -336,7 +341,7 @@ static bool _pumpAction( struct TRACEDecoderEngine *e, struct TRACECPUState *cpu

case 0b11000000 ... 0b11010100:
case 0b11100000 ... 0b11110100: /* Atom format 6, Figure 6-44, Pg 6.307 */
cpu->eatoms = ( c & 0x1f ) + 3;
cpu->eatoms = ( c & 0x1f ) + 4;
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It moves by 3 + 1 because the COUNT value needs to be added

cpu->instCount = cpu->eatoms;
cpu->disposition = ( 1 << ( cpu->eatoms ) ) - 1;

Expand Down Expand Up @@ -404,6 +409,8 @@ static bool _pumpAction( struct TRACEDecoderEngine *e, struct TRACECPUState *cpu
cpu->addr = j->q[match].addr;
retVal = TRACE_EV_MSG_RXED;
_stateChange( cpu, EV_CH_ADDRESS );
_stackQ( j );
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After Exact Match Address the function update_address_regs is called therefore a stackQ is needed

j->q[0].addr = cpu->addr;
break;

case 0b10010101: /* Short address, IS0 short, Figure 6-32, Pg 6-294 */
Expand Down Expand Up @@ -685,7 +692,7 @@ static bool _pumpAction( struct TRACEDecoderEngine *e, struct TRACECPUState *cpu
}
else
{
if ( j->idx == 8 )
if ( j->idx == 9 )
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for j->idx = 2 initialised, adding 7 from above should be 9 instead of 8

{
/* Second byte of IS1 case - mask MSB */
j->q[0].addr = ( j->q[0].addr & ( ~( 0x7F << j->idx ) ) ) | ( ( c & 0x7f ) << ( j->idx ) );
Expand Down
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