Logicademy

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3 repositories

PYNQ-SoC-Builder
Public
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
python automation fpga vhdl verilog xilinx vivado hardware-designs pynq hdl
Python
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GNU Affero General Public License v3.0
•3•3•5•0•Updated Feb 25, 2025Feb 25, 2025
Pluto
Public
RISC-V Assembler in a Jupyter Notebook
Jupyter Notebook
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GNU Affero General Public License v3.0
•0•1•0•0•Updated Oct 29, 2024Oct 29, 2024
HDLGen-ChatGPT
Public
HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
python automation fpga xml vhdl verilog xilinx vivado hardware-designs hdl
Python
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GNU Affero General Public License v3.0
•15•24•11•0•Updated Oct 28, 2024Oct 28, 2024