Merge pull request #65 from muhammadhamza15/mhamza_dev

Modified MIPI testbenches
os-fpga · Sep 27, 2024 · 5253008 · 5253008
2 parents 53d8671 + aeefa2f
commit 5253008
Show file tree

Hide file tree

Showing 2 changed files with 66 additions and 4 deletions.
diff --git a/models_internal/verilog/tb/MIPI_RX_tb.v b/models_internal/verilog/tb/MIPI_RX_tb.v
@@ -29,6 +29,7 @@ module MIPI_RX_tb;
   wire  LP_RX_DN;
 
   real delay;
+  integer error=0;
 
   MIPI_RX # (
     .WIDTH(WIDTH),
@@ -153,6 +154,22 @@ module MIPI_RX_tb;
         end
       end
     join_any
+    repeat(17)@(posedge CLK_IN);
+    if(HS_RX_DATA!=='ha)
+      error=error+1;
+    @(posedge CLK_IN);
+    if(HS_RX_DATA!=='hc)
+      error=error+1;
+    @(posedge CLK_IN);
+    if(HS_RX_DATA!=='hd)
+      error=error+1;
+
+    #2;
+    if(error===0)
+      $display("Test Passed");
+    else
+      $display("Test Failed");
+
     #1000;
     $finish;
 

diff --git a/models_internal/verilog/tb/MIPI_TX_tb.v b/models_internal/verilog/tb/MIPI_TX_tb.v
@@ -28,6 +28,13 @@ module MIPI_TX_tb;
   reg  CHANNEL_BOND_SYNC_IN;
   wire  CHANNEL_BOND_SYNC_OUT;
 
+  reg [WIDTH-1:0] HS_TX_DATA1=0;
+  reg [WIDTH-1:0] HS_TX_DATA2=0;
+  reg [WIDTH-1:0] HS_TX_DATA3=0;
+  reg [WIDTH-1:0] comp_data=0;
+  integer error=0;
+
+
   MIPI_TX # (
     .WIDTH(WIDTH),
     .EN_ODLY(EN_ODLY),
@@ -82,16 +89,54 @@ module MIPI_TX_tb;
 		PLL_LOCK=1;
 		repeat(260)@(posedge RX_CLK);
 		HS_TX_DATA=4'b0101;
+    HS_TX_DATA1=HS_TX_DATA;
 		@(negedge CLK_IN);
 		HS_TX_DATA=$urandom();
+    HS_TX_DATA2=HS_TX_DATA;
 		@(negedge CLK_IN);
 		HS_TX_DATA=$urandom();
-		#1000;
+    HS_TX_DATA3=HS_TX_DATA;
+    @(negedge MIPI_TX_inst.O_SERDES_inst.word_load_en_sync);
+    repeat(4)@(RX_CLK)
+    begin
+      comp_data={comp_data[WIDTH-2:0],TX_DP};
+    end
+    if(comp_data!==HS_TX_DATA1)
+      error=error+1;
+
+    @(negedge MIPI_TX_inst.O_SERDES_inst.word_load_en_sync);
+    repeat(4)@(RX_CLK)
+    begin
+      comp_data={comp_data[WIDTH-2:0],TX_DP};
+    end
+    if(comp_data!==HS_TX_DATA2)
+      error=error+1;
+
+    @(negedge MIPI_TX_inst.O_SERDES_inst.word_load_en_sync);
+    repeat(4)@(RX_CLK)
+    begin
+      comp_data={comp_data[WIDTH-2:0],TX_DP};
+    end
+    if(comp_data!==HS_TX_DATA3)
+      error=error+1;
+
+    #1000;
     HS_EN=0;
     LP_EN=1;
-    @(negedge CLK_IN);
-		TX_LP_DN=$urandom();
-		TX_LP_DP=$urandom();
+    repeat(50)@(negedge CLK_IN)
+    begin
+      TX_LP_DP=$urandom();
+		  TX_LP_DN=~TX_LP_DP;
+      #1;
+      if(TX_LP_DP!==TX_DP || TX_LP_DN!==TX_DN)
+        error=error+1;
+    end
+    #2;
+    if(error===0)
+      $display("Test Passed");
+    else
+      $display("Test Failed");
+
     #1000;
     TX_ODT_EN=1;
     #100;