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Merge pull request #58 from AllahWasya/main
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updated BRAM 36K and 18K models and FIFO 36K tb
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@muhammadhamza15
muhammadhamza15 authored Aug 23, 2024
2 parents 6f78ba5 + b60f8b0 commit 71b9b04
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Showing 5 changed files with 117 additions and 63 deletions.
30 changes: 17 additions & 13 deletions models_internal/verilog/TDP_RAM18KX2.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,6 @@ module TDP_RAM18KX2 #(
output reg [1:0] RPARITY_B2 = {2{1'b0}} // Read parity port B, RAM 2
);


//RAM1
localparam A1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A1);
localparam A1_WRITE_ADDR_WIDTH = calc_depth(A1_DATA_WRITE_WIDTH);
Expand Down Expand Up @@ -168,13 +167,13 @@ module TDP_RAM18KX2 #(
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

end
always @(posedge CLK_B1)
if (WEN_B1) begin
for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin
Expand Down Expand Up @@ -211,12 +210,13 @@ module TDP_RAM18KX2 #(
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
end
endgenerate

Expand Down Expand Up @@ -280,12 +280,13 @@ module TDP_RAM18KX2 #(
#collision_window;
collision_a_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif
end

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -333,13 +334,13 @@ module TDP_RAM18KX2 #(
#collision_window;
collision_b_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

end
// Collision checking
always @(posedge collision_a_write_flag) begin
if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin
Expand Down Expand Up @@ -479,12 +480,13 @@ module TDP_RAM18KX2 #(
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -522,12 +524,13 @@ module TDP_RAM18KX2 #(
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
end
endgenerate

Expand Down Expand Up @@ -591,13 +594,13 @@ module TDP_RAM18KX2 #(
#collision_window;
collision_a2_read_flag = 0;
end
else
`ifndef FIFO
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

end
always @(posedge CLK_B2)
if (WEN_B2) begin
for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin
Expand Down Expand Up @@ -644,12 +647,13 @@ module TDP_RAM18KX2 #(
#collision_window;
collision_b2_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif
end

// Collision checking
always @(posedge collision_a2_write_flag) begin
Expand Down
20 changes: 11 additions & 9 deletions models_internal/verilog/TDP_RAM36K.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -140,13 +140,14 @@ module TDP_RAM36K #(
`endif
end
end
else
`ifndef FIFO
else begin
`ifndef FIFO

// verilator lint_off BLKANDNBLK
RPARITY_A <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif

end

always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -185,12 +186,13 @@ module TDP_RAM36K #(
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B <= 4'bx;
// verilator lint_on BLKANDNBLK
`endif
end
end
endgenerate

Expand Down Expand Up @@ -253,12 +255,13 @@ module TDP_RAM36K #(
#collision_window;
collision_a_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif
end

always @(posedge CLK_B)
if (WEN_B) begin
Expand Down Expand Up @@ -304,13 +307,13 @@ module TDP_RAM36K #(
#collision_window;
collision_b_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B <= 32'bx;
// verilator lint_on BLKANDNBLK
`endif

end

/*
always @(posedge CLK_B)
Expand Down Expand Up @@ -478,8 +481,7 @@ module TDP_RAM36K #(

initial
$timeformat(-9,0," ns", 5);

initial begin
initial begin
case(WRITE_WIDTH_A)
1 ,
2 ,
Expand Down
30 changes: 17 additions & 13 deletions models_internal/verilog/inc/TDP_RAM18KX2.inc.v
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@


//RAM1
localparam A1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A1);
localparam A1_WRITE_ADDR_WIDTH = calc_depth(A1_DATA_WRITE_WIDTH);
Expand Down Expand Up @@ -104,13 +103,13 @@
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif

end
always @(posedge CLK_B1)
if (WEN_B1) begin
for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin
Expand Down Expand Up @@ -147,12 +146,13 @@
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B1 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
end
endgenerate

Expand Down Expand Up @@ -216,12 +216,13 @@
#collision_window;
collision_a_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif
end

always @(posedge CLK_B1)
if (WEN_B1) begin
Expand Down Expand Up @@ -269,13 +270,13 @@
#collision_window;
collision_b_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B1 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

end
// Collision checking
always @(posedge collision_a_write_flag) begin
if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin
Expand Down Expand Up @@ -415,12 +416,13 @@
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_A2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end

always @(posedge CLK_B2)
if (WEN_B2) begin
Expand Down Expand Up @@ -458,12 +460,13 @@
`endif
end
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RPARITY_B2 <= 2'bx;
// verilator lint_on BLKANDNBLK
`endif
end
end
endgenerate

Expand Down Expand Up @@ -527,13 +530,13 @@
#collision_window;
collision_a2_read_flag = 0;
end
else
`ifndef FIFO
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_A2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif

end
always @(posedge CLK_B2)
if (WEN_B2) begin
for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin
Expand Down Expand Up @@ -580,12 +583,13 @@
#collision_window;
collision_b2_read_flag = 0;
end
else
else begin
`ifndef FIFO
// verilator lint_off BLKANDNBLK
RDATA_B2 <= 16'bx;
// verilator lint_on BLKANDNBLK
`endif
end

// Collision checking
always @(posedge collision_a2_write_flag) begin
Expand Down
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