Merge pull request #23 from muhammadhamza15/mhamza_dev

Mhamza dev
os-fpga · Aug 2, 2024 · c214b81 · c214b81
2 parents d8715d2 + ef3d237
commit c214b81
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Showing 72 changed files with 321 additions and 5,420 deletions.
diff --git a/Makefile b/Makefile
@@ -34,7 +34,7 @@ bb_models: $(BB_TARGETS)
 # we need to make TDP_RAM36K.v first as it is used by the FIFO.
 core_sim_models: models_internal/verilog/TDP_RAM36K.v
 
-sim_models: core_sim_models  $(SIM_TARGETS) $(CUST_SIM_TARGETS)
+sim_models: core_sim_models  $(SIM_TARGETS) #$(CUST_SIM_TARGETS)
 
 models_internal/verilog_blackbox/rundir/%.v: specs/%.yaml
 	mkdir -p models_internal/verilog_blackbox/rundir

diff --git a/bin/p4def_to_simv.py b/bin/p4def_to_simv.py
@@ -316,9 +316,10 @@ def main():
         if has_parameters and has_properties:
             outstr += f"module {name} #(\n    "
             outstr += param_str
-            outstr += "`ifdef RAPIDSILICON_INTERNAL\n    ,"
+            #outstr += "`ifdef RAPIDSILICON_INTERNAL\n    ,"
+            outstr += ","
             outstr += prop_str
-            outstr += "`endif // RAPIDSILICON_INTERNAL\n"
+            #outstr += "`endif // RAPIDSILICON_INTERNAL\n"
             outstr += ") (\n"
             stream.write(outstr)
 
@@ -330,11 +331,11 @@ def main():
 
         if not has_parameters and has_properties:
             outstr += f"module {name}\n"
-            outstr += "`ifdef RAPIDSILICON_INTERNAL\n    "
+            #outstr += "`ifdef RAPIDSILICON_INTERNAL\n    "
             outstr += "#(\n"
             outstr += prop_str
             outstr += ")\n"
-            outstr += "`endif // RAPIDSILICON_INTERNAL\n"
+            #outstr += "`endif // RAPIDSILICON_INTERNAL\n"
             outstr += "(\n"
             stream.write(outstr)
 
@@ -475,7 +476,7 @@ def main():
 
         # property checking
         if 'properties' in spec_dict:
-            stream.write('\n`ifdef RAPIDSILICON_INTERNAL\n')
+            #stream.write('\n`ifdef RAPIDSILICON_INTERNAL\n')
             for param in spec_dict["properties"]:
 
                 # determine if property is numeric or not
@@ -514,7 +515,7 @@ def main():
                 stream.write("      end\n")
                 stream.write("    endcase\n")
 
-            stream.write('`endif // RAPIDSILICON_INTERNAL\n')
+            #stream.write('`endif // RAPIDSILICON_INTERNAL\n')
 
         if needs_checking(spec_dict):
             stream.write("\n  end\n")

diff --git a/etc/bb.mako b/etc/bb.mako
@@ -130,9 +130,9 @@ def generate_port_str(port):
 % if has_parameters and has_properties:
 module ${dd['name']} #(
 ${param_str}
-`ifdef RAPIDSILICON_INTERNAL
-  , ${prop_str}
-`endif // RAPIDSILICON_INTERNAL
+##`ifdef RAPIDSILICON_INTERNAL
+,${prop_str}
+##`endif // RAPIDSILICON_INTERNAL
   ) (
 % endif
 ## ONLY PARAMETERS
@@ -144,11 +144,11 @@ ${param_str}
 ## ONLY PROPERTIES
 % if not has_parameters and has_properties:
 module ${dd['name']}
-`ifdef RAPIDSILICON_INTERNAL
+##`ifdef RAPIDSILICON_INTERNAL
   #(
 ${prop_str}
   )
-`endif // RAPIDSILICON_INTERNAL
+##`endif // RAPIDSILICON_INTERNAL
   (
 % endif
 ## NEITHER PARAMETERS NOR PROPERTIES

diff --git a/models_customer/README.txt b/models_customer/README.txt
diff --git a/models_customer/ibis/GeminiPlus-0.0.1.tar.gz b/models_customer/ibis/GeminiPlus-0.0.1.tar.gz
diff --git a/models_customer/verilog/BOOT_CLOCK.v b/models_customer/verilog/BOOT_CLOCK.v
diff --git a/models_customer/verilog/CARRY.v b/models_customer/verilog/CARRY.v
diff --git a/models_customer/verilog/CLK_BUF.v b/models_customer/verilog/CLK_BUF.v
diff --git a/models_customer/verilog/DFFNRE.v b/models_customer/verilog/DFFNRE.v
diff --git a/models_customer/verilog/DFFRE.v b/models_customer/verilog/DFFRE.v