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Merge branch 'main' of github.com:anaszameer/device_modeling
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@anaszameer
anaszameer committed Jul 5, 2024
2 parents f4de1cf + 65b6413 commit e17b8db
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Showing 15 changed files with 187 additions and 89 deletions.
15 changes: 13 additions & 2 deletions models_customer/verilog/DSP19X2.v
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Original file line number Diff line number Diff line change
Expand Up @@ -373,8 +373,8 @@ module DSP19X2 #(

assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
assign DLY_B1 = dly_b1;
assign DLY_B2 = dly_b2;
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;


// If ACC_FIR is greater than 21, result is invalid
Expand All @@ -391,6 +391,17 @@ module DSP19X2 #(
$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
#1 $finish ;
end

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

initial begin
case(DSP_MODE)
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24 changes: 21 additions & 3 deletions models_customer/verilog/DSP38.v
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ module DSP38 #(
input [17:0] B, // 18-bit data input for multiplication
input [5:0] ACC_FIR, // 6-bit left shift A input
output [37:0] Z, // 38-bit data output
output reg [17:0] DLY_B = 18'h00000, // 18-bit B registered output
output reg [17:0] DLY_B, // 18-bit B registered output
input CLK, // Clock
input RESET, // Active high reset
input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient
Expand All @@ -33,6 +33,7 @@ module DSP38 #(
input UNSIGNED_B // Selects signed or unsigned data for B input
);


// registers
reg subtract_reg = 1'b0;
reg [5:0] acc_fir_reg = 6'h00;
Expand Down Expand Up @@ -275,12 +276,18 @@ module DSP38 #(
begin
if(RESET)
begin
DLY_B <= 18'h00000;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= 18'h00000;

z_out_reg <= 38'h00000000;
end
else
begin
DLY_B <= B;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= B;
else
DLY_B <= 18'dx;

z_out_reg <= z_out;
end
end
Expand All @@ -292,6 +299,17 @@ module DSP38 #(
if (ACC_FIR > 43)
$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

initial begin
case(DSP_MODE)
"MULTIPLY" ,
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2 changes: 2 additions & 0 deletions models_customer/verilog/I_DDR.v
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,8 @@ module I_DDR (
Q[1]<=data_pos;
Q[0]<=data_neg;
end
else
Q<=Q;

end

Expand Down
2 changes: 2 additions & 0 deletions models_customer/verilog/O_DDR.v
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Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,8 @@ module O_DDR (
Q <= Q0;
else
Q <= Q1;
else
Q <= Q;
end

endmodule
Expand Down
15 changes: 13 additions & 2 deletions models_internal/verilog/DSP19X2.v
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Original file line number Diff line number Diff line change
Expand Up @@ -373,8 +373,8 @@ module DSP19X2 #(

assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
assign DLY_B1 = dly_b1;
assign DLY_B2 = dly_b2;
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;


// If ACC_FIR is greater than 21, result is invalid
Expand All @@ -391,6 +391,17 @@ module DSP19X2 #(
$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
#1 $finish ;
end

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

initial begin
case(DSP_MODE)
Expand Down
24 changes: 21 additions & 3 deletions models_internal/verilog/DSP38.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ module DSP38 #(
input [17:0] B, // 18-bit data input for multiplication
input [5:0] ACC_FIR, // 6-bit left shift A input
output [37:0] Z, // 38-bit data output
output reg [17:0] DLY_B = 18'h00000, // 18-bit B registered output
output reg [17:0] DLY_B, // 18-bit B registered output
input CLK, // Clock
input RESET, // Active high reset
input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient
Expand All @@ -33,6 +33,7 @@ module DSP38 #(
input UNSIGNED_B // Selects signed or unsigned data for B input
);


// registers
reg subtract_reg = 1'b0;
reg [5:0] acc_fir_reg = 6'h00;
Expand Down Expand Up @@ -275,12 +276,18 @@ module DSP38 #(
begin
if(RESET)
begin
DLY_B <= 18'h00000;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= 18'h00000;

z_out_reg <= 38'h00000000;
end
else
begin
DLY_B <= B;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= B;
else
DLY_B <= 18'dx;

z_out_reg <= z_out;
end
end
Expand All @@ -292,6 +299,17 @@ module DSP38 #(
if (ACC_FIR > 43)
$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

initial begin
case(DSP_MODE)
"MULTIPLY" ,
Expand Down
2 changes: 2 additions & 0 deletions models_internal/verilog/I_DDR.v
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,8 @@ module I_DDR (
Q[1]<=data_pos;
Q[0]<=data_neg;
end
else
Q<=Q;

end

Expand Down
2 changes: 2 additions & 0 deletions models_internal/verilog/O_DDR.v
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Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,8 @@ module O_DDR (
Q <= Q0;
else
Q <= Q1;
else
Q <= Q;
end

endmodule
Expand Down
15 changes: 13 additions & 2 deletions models_internal/verilog/inc/DSP19X2.inc.v
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Original file line number Diff line number Diff line change
Expand Up @@ -331,8 +331,8 @@

assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
assign DLY_B1 = dly_b1;
assign DLY_B2 = dly_b2;
assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;


// If ACC_FIR is greater than 21, result is invalid
Expand All @@ -349,4 +349,15 @@
$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
#1 $finish ;
end

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

22 changes: 20 additions & 2 deletions models_internal/verilog/inc/DSP38.inc.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@


// registers
reg subtract_reg = 1'b0;
reg [5:0] acc_fir_reg = 6'h00;
Expand Down Expand Up @@ -241,12 +242,18 @@
begin
if(RESET)
begin
DLY_B <= 18'h00000;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= 18'h00000;

z_out_reg <= 38'h00000000;
end
else
begin
DLY_B <= B;
if(DSP_MODE== "MULTIPLY_ADD_SUB")
DLY_B <= B;
else
DLY_B <= 18'dx;

z_out_reg <= z_out;
end
end
Expand All @@ -258,3 +265,14 @@
if (ACC_FIR > 43)
$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);

always@(*)
begin
case(DSP_MODE)
"MULTIPLY_ACCUMULATE": begin
if(FEEDBACK>1)
$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
end
endcase

end

2 changes: 2 additions & 0 deletions models_internal/verilog/inc/I_DDR.inc.v
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Original file line number Diff line number Diff line change
Expand Up @@ -34,5 +34,7 @@
Q[1]<=data_pos;
Q[0]<=data_neg;
end
else
Q<=Q;

end
2 changes: 2 additions & 0 deletions models_internal/verilog/inc/O_DDR.inc.v
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Original file line number Diff line number Diff line change
Expand Up @@ -39,5 +39,7 @@
Q <= Q0;
else
Q <= Q1;
else
Q <= Q;
end

76 changes: 38 additions & 38 deletions models_internal/verilog/tb/DSP19x2_tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -456,46 +456,46 @@ module DSP19x2_tb;
$display("ACC SUBTRACTION TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);

// FEEDBACK 3 -> ACC Mult x B
@(negedge CLK);
A1=3;
B1=1;
A2=3;
B2=1;
ACC_FIR=1;
FEEDBACK=3;
LOAD_ACC=1;
SATURATE=0;
SHIFT_RIGHT=0;
ROUND=0;
SUBTRACT=0;
UNSIGNED_A=1;
UNSIGNED_B=1;

if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
repeat(2)@(posedge CLK);
else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
@(posedge CLK);
// @(negedge CLK);
// A1=3;
// B1=1;
// A2=3;
// B2=1;
// ACC_FIR=1;
// FEEDBACK=3;
// LOAD_ACC=1;
// SATURATE=0;
// SHIFT_RIGHT=0;
// ROUND=0;
// SUBTRACT=0;
// UNSIGNED_A=1;
// UNSIGNED_B=1;

// if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
// repeat(2)@(posedge CLK);
// else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
// @(posedge CLK);

@(posedge CLK);
#1;
if(Z1===6 && Z2===6)
$display("ACC MULT TEST PASSED");
else
$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);

@(posedge CLK);
#1;
if(Z1===12 && Z2===12)
$display("ACC MULT TEST PASSED");
else
$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
// @(posedge CLK);
// #1;
// if(Z1===6 && Z2===6)
// $display("ACC MULT TEST PASSED");
// else
// $display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);

// @(posedge CLK);
// #1;
// if(Z1===12 && Z2===12)
// $display("ACC MULT TEST PASSED");
// else
// $display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);

@(posedge CLK);
#1;
if(Z1===18 && Z2===18)
$display("ACC MULT TEST PASSED");
else
$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
// @(posedge CLK);
// #1;
// if(Z1===18 && Z2===18)
// $display("ACC MULT TEST PASSED");
// else
// $display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);

// UNSIGNED SATURATION OVERFLOW
@(negedge CLK);
Expand Down
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