Merge pull request #46 from muhammadhamza15/main

Simulation Models Updates
os-fpga · Jul 15, 2024 · e581cdf · e581cdf
2 parents 29ab76d + 41a966e
commit e581cdf
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Showing 61 changed files with 493 additions and 293 deletions.
diff --git a/bin/p4def_to_simv.py b/bin/p4def_to_simv.py
@@ -444,8 +444,7 @@ def main():
                         format_char = "%d"
 
                     stream.write(f"\n    if (({param} < {minval}) || ({param} > {maxval})) begin\n")
-                    stream.write(f"       $display(\"{name} instance %m {param} set to incorrect value, {format_char}.  Values must be between {minval} and {maxval}.\", {param});\n")
-                    stream.write("    #1 $stop;\n")
+                    stream.write(f"       $fatal(1,\"{name} instance %m {param} set to incorrect value, {format_char}.  Values must be between {minval} and {maxval}.\", {param});\n")
                     stream.write("    end\n")
                     continue
 
@@ -469,8 +468,7 @@ def main():
                 stream.write(f"    case({param})\n")
                 stream.write(f"      {value_list_for_case}: begin end\n")
                 stream.write("      default: begin\n")
-                stream.write(f"        $display(\"\\nError: {name} instance %m has parameter {param} set to {format_char}.  Valid values are {value_list_for_msg}\\n\", {param});\n")
-                stream.write("        #1 $stop ;\n")
+                stream.write(f"        $fatal(1,\"\\nError: {name} instance %m has parameter {param} set to {format_char}.  Valid values are {value_list_for_msg}\\n\", {param});\n")
                 stream.write("      end\n")
                 stream.write("    endcase\n")
 
@@ -490,8 +488,7 @@ def main():
                         format_char = "%d"
 
                     stream.write(f"\n    if (({param} < {minval}) || ({param} > {maxval})) begin\n")
-                    stream.write(f"       $display(\"{name} instance %m {param} set to incorrect value, {format_char}.  Values must be between {minval} and {maxval}.\", {param});\n")
-                    stream.write("    #1 $stop;\n")
+                    stream.write(f"       $fatal(1,\"{name} instance %m {param} set to incorrect value, {format_char}.  Values must be between {minval} and {maxval}.\", {param});\n")
                     stream.write("    end\n")
                     continue
 
@@ -513,8 +510,7 @@ def main():
                 stream.write(f"\n    case({param})\n")
                 stream.write(f"      {value_list_for_case}: begin end\n")
                 stream.write("      default: begin\n")
-                stream.write(f"        $display(\"\\nError: {name} instance %m has parameter {param} set to %s.  Valid values are {value_list_for_msg}\\n\", {param});\n")
-                stream.write("        #1 $stop ;\n")
+                stream.write(f"        $fatal(1,\"\\nError: {name} instance %m has parameter {param} set to %s.  Valid values are {value_list_for_msg}\\n\", {param});\n")
                 stream.write("      end\n")
                 stream.write("    endcase\n")
 

diff --git a/models_customer/verilog/BOOT_CLOCK.v b/models_customer/verilog/BOOT_CLOCK.v
@@ -20,8 +20,7 @@ localparam HALF_PERIOD = PERIOD/2.0;
  initial begin
 
     if ((PERIOD < 16.0) || (PERIOD > 30.0)) begin
-       $display("BOOT_CLOCK instance %m PERIOD set to incorrect value, %f.  Values must be between 16.0 and 30.0.", PERIOD);
-    #1 $stop;
+       $fatal(1,"BOOT_CLOCK instance %m PERIOD set to incorrect value, %f.  Values must be between 16.0 and 30.0.", PERIOD);
     end
 
   end

diff --git a/models_customer/verilog/DSP19X2.v b/models_customer/verilog/DSP19X2.v
@@ -381,23 +381,21 @@ module DSP19X2 #(
 	always @(ACC_FIR)
 		if (ACC_FIR > 21)
 		begin
-			$display("WARNING: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
-			#1 $finish ;
+			$fatal(1,"WARNING: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR);
 		end
 	// If SHIFT_RIGHT is greater than 31, result is invalid
 	always @(SHIFT_RIGHT)
 		if (SHIFT_RIGHT > 31)
 		begin
-			$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
-			#1 $finish ;
+			$fatal(1,"WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
 		end
 
 	always@(*) 
 	begin
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-					$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+					$fatal(1,"\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 
@@ -409,24 +407,21 @@ module DSP19X2 #(
       "MULTIPLY_ADD_SUB" ,
       "MULTIPLY_ACCUMULATE": begin end
       default: begin
-        $display("\nError: DSP19X2 instance %m has parameter DSP_MODE set to %s.  Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP19X2 instance %m has parameter DSP_MODE set to %s.  Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE);
       end
     endcase
     case(OUTPUT_REG_EN)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: DSP19X2 instance %m has parameter OUTPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", OUTPUT_REG_EN);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP19X2 instance %m has parameter OUTPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", OUTPUT_REG_EN);
       end
     endcase
     case(INPUT_REG_EN)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: DSP19X2 instance %m has parameter INPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", INPUT_REG_EN);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP19X2 instance %m has parameter INPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", INPUT_REG_EN);
       end
     endcase
 

diff --git a/models_customer/verilog/DSP38.v b/models_customer/verilog/DSP38.v
@@ -297,14 +297,14 @@ module DSP38 #(
 	// If ACC_FIR is greater than 43, result is invalid
 	always @(ACC_FIR)
 		if (ACC_FIR > 43)
-			$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
+			$fatal(1,"\nWARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
 
 	always@(*) 
 	begin
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-					$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+					$fatal(1,"\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 
@@ -316,24 +316,21 @@ module DSP38 #(
       "MULTIPLY_ADD_SUB" ,
       "MULTIPLY_ACCUMULATE": begin end
       default: begin
-        $display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s.  Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP38 instance %m has parameter DSP_MODE set to %s.  Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE);
       end
     endcase
     case(OUTPUT_REG_EN)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: DSP38 instance %m has parameter OUTPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", OUTPUT_REG_EN);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP38 instance %m has parameter OUTPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", OUTPUT_REG_EN);
       end
     endcase
     case(INPUT_REG_EN)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: DSP38 instance %m has parameter INPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", INPUT_REG_EN);
-        #1 $stop ;
+        $fatal(1,"\nError: DSP38 instance %m has parameter INPUT_REG_EN set to %s.  Valid values are TRUE, FALSE\n", INPUT_REG_EN);
       end
     endcase
 

diff --git a/models_customer/verilog/FIFO18KX2.v b/models_customer/verilog/FIFO18KX2.v
@@ -337,48 +337,42 @@ tdp_ram18kx2_inst
       9 ,
       18: begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH1 set to %d.  Valid values are 9, 18\n", DATA_WRITE_WIDTH1);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH1 set to %d.  Valid values are 9, 18\n", DATA_WRITE_WIDTH1);
       end
     endcase
     case(DATA_READ_WIDTH1)
       9 ,
       18: begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH1 set to %d.  Valid values are 9, 18\n", DATA_READ_WIDTH1);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH1 set to %d.  Valid values are 9, 18\n", DATA_READ_WIDTH1);
       end
     endcase
     case(FIFO_TYPE1)
       "SYNCHRONOUS" ,
       "ASYNCHRONOUS": begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE1 set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE1);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE1 set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE1);
       end
     endcase
     case(DATA_WRITE_WIDTH2)
       9 ,
       18: begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH2 set to %d.  Valid values are 9, 18\n", DATA_WRITE_WIDTH2);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH2 set to %d.  Valid values are 9, 18\n", DATA_WRITE_WIDTH2);
       end
     endcase
     case(DATA_READ_WIDTH2)
       9 ,
       18: begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH2 set to %d.  Valid values are 9, 18\n", DATA_READ_WIDTH2);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH2 set to %d.  Valid values are 9, 18\n", DATA_READ_WIDTH2);
       end
     endcase
     case(FIFO_TYPE2)
       "SYNCHRONOUS" ,
       "ASYNCHRONOUS": begin end
       default: begin
-        $display("\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE2 set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE2);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE2 set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE2);
       end
     endcase
 

diff --git a/models_customer/verilog/FIFO36K.v b/models_customer/verilog/FIFO36K.v
@@ -202,25 +202,22 @@ module FIFO36K #(
       18 ,
       36: begin end
       default: begin
-        $display("\nError: FIFO36K instance %m has parameter DATA_WRITE_WIDTH set to %d.  Valid values are 9, 18, 36\n", DATA_WRITE_WIDTH);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO36K instance %m has parameter DATA_WRITE_WIDTH set to %d.  Valid values are 9, 18, 36\n", DATA_WRITE_WIDTH);
       end
     endcase
     case(DATA_READ_WIDTH)
       9 ,
       18 ,
       36: begin end
       default: begin
-        $display("\nError: FIFO36K instance %m has parameter DATA_READ_WIDTH set to %d.  Valid values are 9, 18, 36\n", DATA_READ_WIDTH);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO36K instance %m has parameter DATA_READ_WIDTH set to %d.  Valid values are 9, 18, 36\n", DATA_READ_WIDTH);
       end
     endcase
     case(FIFO_TYPE)
       "SYNCHRONOUS" ,
       "ASYNCHRONOUS": begin end
       default: begin
-        $display("\nError: FIFO36K instance %m has parameter FIFO_TYPE set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE);
-        #1 $stop ;
+        $fatal(1,"\nError: FIFO36K instance %m has parameter FIFO_TYPE set to %s.  Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE);
       end
     endcase
 

diff --git a/models_customer/verilog/I_BUF.v b/models_customer/verilog/I_BUF.v
@@ -31,8 +31,7 @@ module I_BUF #(
       "PULLUP" ,
       "PULLDOWN": begin end
       default: begin
-        $display("\nError: I_BUF instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
-        #1 $stop ;
+        $fatal(1,"\nError: I_BUF instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
       end
     endcase
 

diff --git a/models_customer/verilog/I_BUF_DS.v b/models_customer/verilog/I_BUF_DS.v
@@ -44,8 +44,7 @@ module I_BUF_DS #(
       "PULLUP" ,
       "PULLDOWN": begin end
       default: begin
-        $display("\nError: I_BUF_DS instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
-        #1 $stop ;
+        $fatal(1,"\nError: I_BUF_DS instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
       end
     endcase
     case(IOSTANDARD)
@@ -66,16 +65,14 @@ module I_BUF_DS #(
       "SSTL_18_HP_DIFF" ,
       "SSTL_18_HR_DIFF": begin end
       default: begin
-        $display("\nError: I_BUF_DS instance %m has parameter IOSTANDARD set to %s.  Valid values are DEFAULT, BLVDS_DIFF, LVDS_HP_DIFF, LVDS_HR_DIFF, LVPECL_25_DIFF, LVPECL_33_DIFF, HSTL_12_DIFF, HSTL_15_DIFF, HSUL_12_DIFF, MIPI_DIFF, POD_12_DIFF, RSDS_DIFF, SLVS_DIFF, SSTL_15_DIFF, SSTL_18_HP_DIFF, SSTL_18_HR_DIFF\n", IOSTANDARD);
-        #1 $stop ;
+        $fatal(1,"\nError: I_BUF_DS instance %m has parameter IOSTANDARD set to %s.  Valid values are DEFAULT, BLVDS_DIFF, LVDS_HP_DIFF, LVDS_HR_DIFF, LVPECL_25_DIFF, LVPECL_33_DIFF, HSTL_12_DIFF, HSTL_15_DIFF, HSUL_12_DIFF, MIPI_DIFF, POD_12_DIFF, RSDS_DIFF, SLVS_DIFF, SSTL_15_DIFF, SSTL_18_HP_DIFF, SSTL_18_HR_DIFF\n", IOSTANDARD);
       end
     endcase
     case(DIFFERENTIAL_TERMINATION)
       "TRUE" ,
       "FALSE": begin end
       default: begin
-        $display("\nError: I_BUF_DS instance %m has parameter DIFFERENTIAL_TERMINATION set to %s.  Valid values are TRUE, FALSE\n", DIFFERENTIAL_TERMINATION);
-        #1 $stop ;
+        $fatal(1,"\nError: I_BUF_DS instance %m has parameter DIFFERENTIAL_TERMINATION set to %s.  Valid values are TRUE, FALSE\n", DIFFERENTIAL_TERMINATION);
       end
     endcase
 

diff --git a/models_customer/verilog/I_DELAY.v b/models_customer/verilog/I_DELAY.v
@@ -59,8 +59,7 @@ assign #(30.0ps + (21.56ps*dly_tap_val)) O = I;			// Adjusted Delay for TT corne
  initial begin
 
     if ((DELAY < 0) || (DELAY > 63)) begin
-       $display("I_DELAY instance %m DELAY set to incorrect value, %d.  Values must be between 0 and 63.", DELAY);
-    #1 $stop;
+       $fatal(1,"I_DELAY instance %m DELAY set to incorrect value, %d.  Values must be between 0 and 63.", DELAY);
     end
 
   end

diff --git a/models_customer/verilog/I_FAB.v b/models_customer/verilog/I_FAB.v
@@ -0,0 +1,19 @@
+`timescale 1ns/1ps
+`celldefine
+//
+// I_FAB simulation model
+// Marker Buffer for periphery to fabric transition
+//
+// Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
+//
+
+module I_FAB (
+  input I, // Input
+  output O // Output
+);
+
+assign O = I ;
+
+
+endmodule
+`endcelldefine
diff --git a/models_customer/verilog/I_SERDES.v b/models_customer/verilog/I_SERDES.v
@@ -758,22 +758,19 @@ assign DATA_VALID=!des_fifo_empty;
       "SDR" ,
       "DDR": begin end
       default: begin
-        $display("\nError: I_SERDES instance %m has parameter DATA_RATE set to %s.  Valid values are SDR, DDR\n", DATA_RATE);
-        #1 $stop ;
+        $fatal(1,"\nError: I_SERDES instance %m has parameter DATA_RATE set to %s.  Valid values are SDR, DDR\n", DATA_RATE);
       end
     endcase
 
     if ((WIDTH < 3) || (WIDTH > 10)) begin
-       $display("I_SERDES instance %m WIDTH set to incorrect value, %d.  Values must be between 3 and 10.", WIDTH);
-    #1 $stop;
+       $fatal(1,"I_SERDES instance %m WIDTH set to incorrect value, %d.  Values must be between 3 and 10.", WIDTH);
     end
     case(DPA_MODE)
       "NONE" ,
       "DPA" ,
       "CDR": begin end
       default: begin
-        $display("\nError: I_SERDES instance %m has parameter DPA_MODE set to %s.  Valid values are NONE, DPA, CDR\n", DPA_MODE);
-        #1 $stop ;
+        $fatal(1,"\nError: I_SERDES instance %m has parameter DPA_MODE set to %s.  Valid values are NONE, DPA, CDR\n", DPA_MODE);
       end
     endcase
 

diff --git a/models_customer/verilog/O_BUFT.v b/models_customer/verilog/O_BUFT.v
@@ -31,8 +31,7 @@ module O_BUFT #(
       "PULLUP" ,
       "PULLDOWN": begin end
       default: begin
-        $display("\nError: O_BUFT instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
-        #1 $stop ;
+        $fatal(1,"\nError: O_BUFT instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
       end
     endcase
 

diff --git a/models_customer/verilog/O_BUFT_DS.v b/models_customer/verilog/O_BUFT_DS.v
@@ -35,8 +35,7 @@ module O_BUFT_DS #(
       "PULLUP" ,
       "PULLDOWN": begin end
       default: begin
-        $display("\nError: O_BUFT_DS instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
-        #1 $stop ;
+        $fatal(1,"\nError: O_BUFT_DS instance %m has parameter WEAK_KEEPER set to %s.  Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER);
       end
     endcase
 

diff --git a/models_customer/verilog/O_DELAY.v b/models_customer/verilog/O_DELAY.v
@@ -59,8 +59,7 @@ assign #(30.0ps + (21.56ps*dly_tap_val)) O = I;				// Adjusted Delay for TT corn
  initial begin
 
     if ((DELAY < 0) || (DELAY > 63)) begin
-       $display("O_DELAY instance %m DELAY set to incorrect value, %d.  Values must be between 0 and 63.", DELAY);
-    #1 $stop;
+       $fatal(1,"O_DELAY instance %m DELAY set to incorrect value, %d.  Values must be between 0 and 63.", DELAY);
     end
 
   end

diff --git a/models_customer/verilog/O_FAB.v b/models_customer/verilog/O_FAB.v
@@ -0,0 +1,18 @@
+`timescale 1ns/1ps
+`celldefine
+//
+// O_FAB simulation model
+// Marker Buffer for fabric to periphery transition
+//
+// Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
+//
+
+module O_FAB (
+  input I, // Input
+  output O // Output
+);
+
+assign O = I ;
+
+endmodule
+`endcelldefine
diff --git a/models_customer/verilog/O_SERDES.v b/models_customer/verilog/O_SERDES.v
@@ -244,14 +244,12 @@ module O_SERDES #(
       "SDR" ,
       "DDR": begin end
       default: begin
-        $display("\nError: O_SERDES instance %m has parameter DATA_RATE set to %s.  Valid values are SDR, DDR\n", DATA_RATE);
-        #1 $stop ;
+        $fatal(1,"\nError: O_SERDES instance %m has parameter DATA_RATE set to %s.  Valid values are SDR, DDR\n", DATA_RATE);
       end
     endcase
 
     if ((WIDTH < 3) || (WIDTH > 10)) begin
-       $display("O_SERDES instance %m WIDTH set to incorrect value, %d.  Values must be between 3 and 10.", WIDTH);
-    #1 $stop;
+       $fatal(1,"O_SERDES instance %m WIDTH set to incorrect value, %d.  Values must be between 3 and 10.", WIDTH);
     end
 
   end