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Fixed scoreboard race condition
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otoomey committed Feb 26, 2024
1 parent ff67933 commit 96a7938
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Showing 3 changed files with 31 additions and 32 deletions.
6 changes: 5 additions & 1 deletion hw/snitch_cluster/src/snitch_fp_ss.sv
Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,11 @@ module snitch_fp_ss import snitch_pkg::*; #(
.data_o ( acc_req_q )
);

assign sb_tests = {fpr_raddr[0], fpr_raddr[1], fpr_raddr[2], rd};
assign sb_tests[0] = fpr_raddr[0];
assign sb_tests[1] = fpr_raddr[1];
assign sb_tests[2] = fpr_raddr[2];
assign sb_tests[3] = rd;
// assign sb_tests = {rd, fpr_raddr[2], fpr_raddr[1], fpr_raddr[0]};
snitch_sb #(
.AddrWidth(5),
.Depth(ScoreboardDepth),
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51 changes: 23 additions & 28 deletions hw/snitch_cluster/src/snitch_sb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,14 @@ module snitch_sb import snitch_pkg::*; #(
output fpu_sb_trace_port_t trace_port_o
);

addr_t [Depth-1:0] scoreboard;
logic [Depth-1:0] occupied;
logic [Depth-1:0] next_index;
addr_t [Depth-1:0] scoreboard_q, scoreboard_d;
logic [Depth-1:0] occupied_q, occupied_d;
logic [AddrWidth-1:0] next_index;
logic [NumTestAddrs-1:0][Depth-1:0] test_checks;

`FFAR(scoreboard_q, scoreboard_d, '0, clk_i, rst_i)
`FFAR(occupied_q, occupied_d, '0, clk_i, rst_i)

// keep track of which indices in the scoreboard are free
snitch_sb_ipool #(
.Depth(Depth)
Expand All @@ -41,39 +44,31 @@ module snitch_sb import snitch_pkg::*; #(
);

// write logic
always_ff @(posedge clk_i) begin
if (full_o && push_valid_i) begin
$display("Warning! attempted to push when full: %d->%b", push_rd_addr_i, next_index);
always_comb begin
occupied_d = occupied_q;
scoreboard_d = scoreboard_q;
if (push_valid_i) begin
scoreboard_d[next_index] = push_rd_addr_i;
occupied_d[next_index] = 1;
end
if (pop_valid_i) begin
occupied_d[pop_index_i] = 0;
end
if (i_indices.usage_o == Depth & pop_valid_i) begin
$display("Warning! attempted to pop when empty: %b", pop_index_i);
end

always_ff @(posedge clk_i) begin
if (push_valid_i & occupied_q[next_index]) begin
$display("Warning! attempted to push to occupied address: %d->%d", push_rd_addr_i, next_index);

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L61

Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:61 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
end
for (int unsigned i = 0; i < Depth; i++) begin
if (push_valid_i & next_index[i]) begin
if (occupied[i]) begin
$display("Warning! attempted to push to occupied address");
end
// $display("Pushing %d to index %d", push_rd_addr_i, i);
scoreboard[i] <= push_rd_addr_i;
occupied[i] <= 1;
end
if (pop_valid_i & pop_index_i[i]) begin
if (occupied[i] != 1) begin
$display("Warning! attempted to clear free address");
end
occupied[i] <= 0;
// $display("Popping index %d", i);
end
// $display("test checks %d: %x", i, test_checks[i]);
// $display("mem %d: %x", i, scoreboard[i]);
// $display("occ %d: %x", i, occupied[i]);
if (pop_valid_i & ~occupied_q[pop_index_i]) begin
$display("Warning! attempted to pop unoccupied address: %d", pop_index_i);
end
end

// test logic
for (genvar j = 0; j < NumTestAddrs; j++) begin

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L69

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:69 column:47}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
for (genvar i = 0; i < Depth; i++) begin

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L70

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:70 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
assign test_checks[j][i] = (scoreboard[i] == test_addr_i[j]) & occupied[i];
assign test_checks[j][i] = (scoreboard_q[i] == test_addr_i[j]) & occupied_q[i];
end
end

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6 changes: 3 additions & 3 deletions hw/snitch_cluster/src/snitch_sb_ipool.sv
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ module snitch_sb_ipool #(
parameter int unsigned Depth = 8, // depth can be arbitrary from 0 to 2**32

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parameter [Depth-1:0] ResetState [Depth-1:0] = '0,

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4

Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:4 column:27}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4

Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:4 column:39}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// DO NOT OVERWRITE THIS PARAMETER
parameter type dtype = logic [Depth-1:0],
parameter type dtype = logic [$clog2(Depth)-1:0],
parameter int unsigned AddrDepth = (Depth > 1) ? $clog2(Depth) : 1
)(
input logic clk_i, // Clock
Expand Down Expand Up @@ -102,7 +102,7 @@ module snitch_sb_ipool #(
for (genvar i = 0; i < Depth; i++) begin

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L102

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:102 column:40}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
mem_q[i] <= 1 << i;
mem_q[i] <= i;
end else if (!gate_clock) begin
mem_q[i] <= mem_n[i];
end
Expand All @@ -112,8 +112,8 @@ module snitch_sb_ipool #(
// needed for simulation
for (genvar i = 0; i < Depth; i++) begin

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L113

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:113 column:40}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
initial begin
mem_q[i] = i;
read_pointer_q = '0;
mem_q[i] = 1 << i;
write_pointer_q = '0;
status_cnt_q = FifoDepth[AddrDepth:0];
// $display("mem_q[%d]=%d", i, mem_q[i]);
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