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@otoomey
otoomey committed Mar 4, 2024
1 parent 20d1e8e commit da5bb06
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50 changes: 29 additions & 21 deletions hw/snitch_cluster/src/snitch_fp_ss.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
parameter type addr_t = logic [AddrWidth-1:0],
parameter type data_t = logic [DataWidth-1:0],
parameter int unsigned RegAddrWidth = TCDMMemAddrWidth+2,
parameter int unsigned RegPrefixWidth = TCDMMemAddrWidth+2-5,
parameter int unsigned RegPrefixWidth = RegAddrWidth-5,
parameter type regaddr_t = logic [RegAddrWidth-1:0]
) (
input logic clk_i,
Expand Down Expand Up @@ -103,17 +103,17 @@ module snitch_fp_ss import snitch_pkg::*; #(
`FFLAR(ssr_active_q, Xssr & ssr_active_d, ssr_active_ena, 1'b0, clk_i, rst_i)

function [RegAddrWidth-1:0] reg_addr;

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L105 

Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]
Raw output 
message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:105 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
input [4:0] reg_name;
input [4:0][RegPrefixWidth-1:0] offsets;
input [4:0] reg_name;
// 8 adjacent registers appear in the same bank
begin
reg_addr = reg_addr_from_offset(offsets[reg_name[4:3]], reg_name);
reg_addr = reg_addr_from_offset(.offset(offsets[reg_name[4:3]]), .reg_name(reg_name));
end
endfunction

function [RegAddrWidth-1:0] reg_addr_from_offset;

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L114 

Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]
Raw output 
message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:114 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
input [4:0] reg_name;
input [RegPrefixWidth-1:0] offset;
input [4:0] reg_name;
// 8 adjacent registers appear in the same bank
begin
reg_addr_from_offset = {offset, reg_name[2:0], reg_name[4:3]};
Expand All @@ -131,7 +131,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
tag_t lsu_tag_in, lsu_tag_out;

// scoreboard
logic [3:0][4:0] sb_tests;
regaddr_t [3:0] sb_tests;
logic [3:0] sb_collision;
logic sb_full;

Expand Down Expand Up @@ -177,7 +177,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
logic [ScoreboardDepth-1:0] sb_pop_index;
} wr_tag_t;

regaddr_t rs1, rs2, rs3;
logic [4:0] rs1, rs2, rs3;

// LSU
typedef enum logic [1:0] {
Expand All @@ -188,6 +188,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
} ls_size_e;


logic [2:0][4:0] fprs;
regaddr_t [2:0] fpr_raddr;
logic dst_ready;

Expand Down Expand Up @@ -289,12 +290,12 @@ module snitch_fp_ss import snitch_pkg::*; #(
assign vfpr_tag_in.data_arga = acc_req_q.data_arga;
assign vfpr_tag_in.data_argb = acc_req_q.data_argb;
assign vfpr_tag_in.data_argc = acc_req_q.data_argc;
assign vfpr_tag_in.rd_offset = cfg_offset[vfpr_tag_in.rd[4:3]]; // TODO
assign vfpr_tag_in.rd_prefix = cfg_offset[vfpr_tag_in.rd[4:3]];

assign vfpr_tag_in.rd = acc_req_q.data_op[11:7];
assign rs1 = reg_addr(.offsets(cfg_offset), .reg_name(acc_req_q.data_op[19:15]));
assign rs2 = reg_addr(.offsets(cfg_offset), .reg_name(acc_req_q.data_op[24:20]));
assign rs3 = reg_addr(.offsets(cfg_offset), .reg_name(acc_req_q.data_op[31:27]));
assign rs1 = acc_req_q.data_op[19:15];
assign rs2 = acc_req_q.data_op[24:20];
assign rs3 = acc_req_q.data_op[31:27];

assign sb_tests[0] = fpr_raddr[0];
assign sb_tests[1] = fpr_raddr[1];
Expand All @@ -304,13 +305,13 @@ module snitch_fp_ss import snitch_pkg::*; #(

logic sb_push_valid;
snitch_sb #(
.AddrWidth(5),
.AddrWidth(RegAddrWidth),
.Depth(ScoreboardDepth),
.NumTestAddrs(4)
) i_sb (
.clk_i,
.rst_i,
.push_rd_addr_i(vfpr_tag_in.rd),
.push_rd_addr_i(reg_addr(.offsets(cfg_offset), .reg_name(vfpr_tag_in.rd))),
.push_valid_i(sb_push_valid),
.entry_index_o(vfpr_tag_in.sb_pop_index),
.pop_index_i(sb_pop_index),
Expand Down Expand Up @@ -2560,13 +2561,14 @@ module snitch_fp_ss import snitch_pkg::*; #(
end

logic [2:0][DataWidth-1:0] vfpr_rdata;
regaddr_t [2:0] reg_addrs;
logic [2:0][AddrWidth-1:0] reg_addrs;
assign reg_addrs[0] = {fpr_raddr[0], 3'b0};
assign reg_addrs[1] = {fpr_raddr[1], 3'b0};
assign reg_addrs[2] = {fpr_raddr[2], 3'b0};

snitch_vfpr #(
.DataWidth(DataWidth),
.AddrWidth(AddrWidth),
.TCDMMemAddrWidth(TCDMMemAddrWidth),

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2572 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2572 column:41}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2572 column:41} end:{line:2573}} text:"    .TCDMMemAddrWidth(TCDMMemAddrWidth),\n"}
.tcdm_req_t(tcdm_req_t),
.tcdm_rsp_t(tcdm_rsp_t),
Expand Down Expand Up @@ -2605,24 +2607,30 @@ module snitch_fp_ss import snitch_pkg::*; #(

// Mux address lines as operands for the FPU can be mangled
always_comb begin
fpr_raddr[0] = rs1;
fpr_raddr[1] = rs2;
fpr_raddr[2] = rs3;
fprs[0] = rs1;
fpr_raddr[0] = reg_addr(.offsets(cfg_offset), .reg_name(rs1));
fprs[1] = rs2;
fpr_raddr[1] = reg_addr(.offsets(cfg_offset), .reg_name(rs2));
fprs[2] = rs3;
fpr_raddr[2] = reg_addr(.offsets(cfg_offset), .reg_name(rs3));

unique case (vfpr_tag_in.op_select[1])
RegA: begin
fpr_raddr[1] = rs1;
fprs[1] = rs1;
fpr_raddr[1] = reg_addr(.offsets(cfg_offset), .reg_name(rs1));;

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2620 

Do not use consecutive null statements like ';;'. [Style: redundant-semicolons] [forbid-consecutive-null-statements]
Raw output 
message:"Do not use consecutive null statements like ';;'. [Style: redundant-semicolons] [forbid-consecutive-null-statements]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2620 column:71}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2620 column:71} end:{line:2621}} text:"        fpr_raddr[1] = reg_addr(.offsets(cfg_offset), .reg_name(rs1));\n"}
end
default:;
endcase

unique case (vfpr_tag_in.op_select[2])
RegB,
RegBRep: begin
fpr_raddr[2] = rs2;
fprs[2] = rs2;
fpr_raddr[2] = reg_addr(.offsets(cfg_offset), .reg_name(rs2));
end
RegDest: begin
fpr_raddr[2] = vfpr_tag_in.rd;
fprs[2] = vfpr_tag_in.rd;
fpr_raddr[2] = reg_addr(.offsets(cfg_offset), .reg_name(vfpr_tag_in.rd));
end
default:;
endcase
Expand Down Expand Up @@ -2755,12 +2763,12 @@ module snitch_fp_ss import snitch_pkg::*; #(
wr_tag_t wr_fpu, wr_lsu, wr_acc, wr_out;

assign wr_fpu.data = fpu_result;
assign wr_fpu.addr = reg_addr_from_offset(fpu_tag_out.rd_prefix, fpu_tag_out.rd);
assign wr_fpu.addr = reg_addr_from_offset(.offset(fpu_tag_out.rd_prefix), .reg_name(fpu_tag_out.rd));

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2766 

Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2766 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
assign wr_fpu.pop_sb = 1'b1;
assign wr_fpu.sb_pop_index = fpu_tag_out.sb_pop_index;

assign wr_lsu.data = ld_result;
assign wr_lsu.addr = reg_addr_from_offset(lsu_tag_out.rd_prefix, lsu_tag_out.rd);
assign wr_lsu.addr = reg_addr_from_offset(.offset(lsu_tag_out.rd_prefix), .reg_name(lsu_tag_out.rd));

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[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2771 

Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2771 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
assign wr_lsu.pop_sb = 1'b1;
assign wr_lsu.sb_pop_index = lsu_tag_out.sb_pop_index;

Expand Down
22 changes: 0 additions & 22 deletions hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -108,12 +108,6 @@ module snitch_tcdm_interconnect #(
assign mem_req_o[i].q = out_req[i];
end

initial begin
if (NumInp == 1 && NumOut == 4) begin
$display("- ic: ByteOffset=%d, SelWidth=%d, InWidth=%d, MemAddrWidth=%d, RealAddrWidth=%d", ByteOffset, SelWidth, $bits(req_i[0].q.addr), MemAddrWidth, $bits(req_i[0].q.addr[ByteOffset+SelWidth+:MemAddrWidth]));
end
end

// ------------
// Request Side
// ------------
Expand Down Expand Up @@ -281,20 +275,4 @@ module snitch_tcdm_interconnect #(
assign rsp_o[i].p_valid = out_rsp_mux.valid;
end


always @(posedge clk_i) begin
// if a transactions is happening
if (|req_q_valid_flat & |rsp_q_ready_flat) begin
$write("- ric: ");
end
foreach (bank_select[i]) begin
if (req_q_valid_flat[i] && rsp_q_ready_flat[i]) begin
$write("[%2d:%x]->[%2d:%x=%x=%x] ", i, req_i[i].q.addr, bank_select[i], in_req[i].addr, out_req[bank_select[i]].addr, mem_req_o[bank_select[i]].q.addr);
end
end
if (|req_q_valid_flat & |rsp_q_ready_flat) begin
$write("\n");
end
end

endmodule
7 changes: 1 addition & 6 deletions hw/snitch_cluster/src/snitch_vfpr.sv
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
module snitch_vfpr import snitch_pkg::*; #(

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 FAILED: File does not start with comment
parameter int unsigned DataWidth = 0,
parameter int unsigned AddrWidth = 0,
parameter int unsigned TCDMMemAddrWidth = 0,
parameter type tcdm_req_t = logic,
parameter type tcdm_rsp_t = logic,
Expand All @@ -8,7 +9,6 @@ module snitch_vfpr import snitch_pkg::*; #(
parameter type mem_rsp_t = logic,
parameter type tag_t = logic,
// derived parameters
parameter int unsigned AddrWidth = TCDMMemAddrWidth + 2,
parameter type addr_t = logic [AddrWidth-1:0],
parameter type data_t = logic [DataWidth-1:0]
) (
Expand Down Expand Up @@ -186,11 +186,6 @@ module snitch_vfpr import snitch_pkg::*; #(
.oup_ready_i(rready_i)
);

initial begin
$display("vfpr mem addr width %d, data width %d", TCDMMemAddrWidth, DataWidth);
$display("mem req addr width: %d", $bits(mem_req_o[0].q.addr));
end

// always @(posedge clk_i) begin
// // if a transactions is happening
// if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[0].q_valid) begin
Expand Down

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