Switched to modified interconnect #6
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (27)
hw/snitch_cluster/src/snitch_tcdm_router.sv|121 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_tcdm_router.sv|147 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_tcdm_router.sv|148 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_tcdm_router.sv|153 col 1| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_tcdm_router.sv|161 col 101| Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
hw/snitch/src/snitch_pkg.sv|380 col 101| Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_fp_ss.sv|93 col 14| Explicitly define a storage type for every parameter and localparam, (ScoreboardDepth). [Style: constants] [explicit-parameter-storage-type]
hw/snitch_cluster/src/snitch_fp_ss.sv|306 col 167| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_tcdm_interconnect.sv|113 col 101| Line length exceeds max: 100; is: 217 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_tcdm_interconnect.sv|292 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_sb.sv|61 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/snitch_cluster/src/snitch_sb.sv|69 col 47| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_sb.sv|70 col 44| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_sb.sv|76 col 47| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_sb.sv|91 col 11| File must end with a newline. [Style: posix-file-endings] [posix-eof]
hw/snitch_cluster/src/snitch_vfpr.sv|61 col 10| File must end with a newline. [Style: posix-file-endings] [posix-eof]
hw/snitch_cluster/src/snitch_sb_ipool.sv|4 col 27| Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]
hw/snitch_cluster/src/snitch_sb_ipool.sv|4 col 39| Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
hw/snitch_cluster/src/snitch_sb_ipool.sv|102 col 40| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_sb_ipool.sv|113 col 40| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_sb_ipool.sv|122 col 10| File must end with a newline. [Style: posix-file-endings] [posix-eof]
hw/snitch_cluster/src/snitch_cluster.sv|743 col 23| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_cluster.sv|798 col 13| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_cluster.sv|816 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_cluster.sv|861 col 13| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster/src/snitch_cluster.sv|869 col 29| Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
hw/snitch_cluster/src/snitch_cluster.sv|997 col 18| All generate block statements must have a label [Style: generate-statements] [generate-label]
Filtered Findings (0)
Annotations
Check warning on line 121 in hw/snitch_cluster/src/snitch_tcdm_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L121
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_router.sv" range:{start:{line:121 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:121 column:1} end:{line:122}} text:"\n"}
Check warning on line 147 in hw/snitch_cluster/src/snitch_tcdm_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L147
Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_router.sv" range:{start:{line:147 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 148 in hw/snitch_cluster/src/snitch_tcdm_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L148
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_router.sv" range:{start:{line:148 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 153 in hw/snitch_cluster/src/snitch_tcdm_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L153
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_router.sv" range:{start:{line:153 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:153 column:1} end:{line:154}} text:"\n"}
Check warning on line 161 in hw/snitch_cluster/src/snitch_tcdm_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_router.sv#L161
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_router.sv" range:{start:{line:161 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 380 in hw/snitch/src/snitch_pkg.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch/src/snitch_pkg.sv#L380
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]" location:{path:"./hw/snitch/src/snitch_pkg.sv" range:{start:{line:380 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 93 in hw/snitch_cluster/src/snitch_fp_ss.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L93
Explicitly define a storage type for every parameter and localparam, (ScoreboardDepth). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ScoreboardDepth). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:93 column:14}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 306 in hw/snitch_cluster/src/snitch_fp_ss.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L306
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:306 column:167}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:306 column:167} end:{line:307}} text:" // $display(\"fifo %b %b %b %b %b\", i_sb.i_indices.mem_q[0], i_sb.i_indices.mem_q[1], i_sb.i_indices.mem_q[2], i_sb.i_indices.mem_q[3], i_sb.i_indices.mem_q[4]);\n"}
Check warning on line 113 in hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L113
Line length exceeds max: 100; is: 217 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 217 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_interconnect.sv" range:{start:{line:113 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 292 in hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_tcdm_interconnect.sv#L292
Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_tcdm_interconnect.sv" range:{start:{line:292 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 61 in hw/snitch_cluster/src/snitch_sb.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L61
Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:61 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 69 in hw/snitch_cluster/src/snitch_sb.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L69
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:69 column:47}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 70 in hw/snitch_cluster/src/snitch_sb.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L70
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:70 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 76 in hw/snitch_cluster/src/snitch_sb.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L76
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:76 column:47}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 91 in hw/snitch_cluster/src/snitch_sb.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb.sv#L91
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"./hw/snitch_cluster/src/snitch_sb.sv" range:{start:{line:91 column:11}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:91 column:11} end:{line:92}} text:"endmodule;\n"}
Check warning on line 61 in hw/snitch_cluster/src/snitch_vfpr.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_vfpr.sv#L61
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"./hw/snitch_cluster/src/snitch_vfpr.sv" range:{start:{line:61 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:61 column:10} end:{line:62}} text:"endmodule\n"}
Check warning on line 4 in hw/snitch_cluster/src/snitch_sb_ipool.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4
Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ResetState). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:4 column:27}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 4 in hw/snitch_cluster/src/snitch_sb_ipool.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L4
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:4 column:39}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 102 in hw/snitch_cluster/src/snitch_sb_ipool.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L102
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:102 column:40}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 113 in hw/snitch_cluster/src/snitch_sb_ipool.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L113
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:113 column:40}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 122 in hw/snitch_cluster/src/snitch_sb_ipool.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_sb_ipool.sv#L122
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"./hw/snitch_cluster/src/snitch_sb_ipool.sv" range:{start:{line:122 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:122 column:10} end:{line:123}} text:"endmodule\n"}
Check warning on line 743 in hw/snitch_cluster/src/snitch_cluster.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L743
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_cluster.sv" range:{start:{line:743 column:23}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:743 column:23} end:{line:744}} text:" .NumPorts (1),\n"}
Check warning on line 798 in hw/snitch_cluster/src/snitch_cluster.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L798
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_cluster.sv" range:{start:{line:798 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 816 in hw/snitch_cluster/src/snitch_cluster.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L816
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_cluster.sv" range:{start:{line:816 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 861 in hw/snitch_cluster/src/snitch_cluster.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster/src/snitch_cluster.sv#L861
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./hw/snitch_cluster/src/snitch_cluster.sv" range:{start:{line:861 column:13}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}