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README.md

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Introduction

read me first

Quick syntax rules to push into the library:

  • snake_case
  • remove tab to white space
  • use of suffix for entity's signal following simple rules: _i, _o and _io respectively for input, output and inout
  • entity, architecture, package, procedure, function, etc... ends as such: end entity; end architecture, etc...
  • use of prefix to gather signal corresponding to same interface like: adc_clk_i, adc_data_i, adc_vld_i...
  • name of architecture: behav, struc, rtl
  • when strcutural architecture would be nice to link components with signal's prefixe name such as: fifo2filter_* (e.g. component A to component B: compa2compb_)

Packages

psi_common_array_pkg

This package defines various array types that are not defined by VHDL natively. Some of these definitions are no more required in VHDL 2008 but since VHDL 2008 is not yet fully synthesizable, the package is kept.

psi_common_logic_pkg

This package contains various logic functions (e.g. combinatorial conversions) that can be synthesized.

psi_common_axi_pkg

This package contains record definitions to allow representing a complete AXI interface including all ports by only two records (one in each direction). This helps improving the readability of entities with AXI interfaces.

psi_common_math_pkg

This package contains various mathematical functions (e.g. log2). The functions are meant for calculating compile-time constants (i.e. constants, port-widths, etc.). They can potentially be synthesized as combinatorial functions but this is neither guaranteed nor will it lead to optimal results.

List of components available

Memory components

Component Source Description
Simple dual port RAM psi_common_sdp_ram.vhd link
Simple dual port RAM with byte enable psi_common_sp_ram_be.vhd link
True Dual port RAM psi_common_tdp_ram.vhd link
True dual port RAM with byte enable psi_common_tdp_ram_be.vhd link

FIFO components

Component Source Description
Asynchronous FIFO psi_common_async_fifo.vhd link
Synchronous FIFO psi_common_sync_fifo.vhd link

Clock domain crossing (CDC) components

Component Source Description
Pulse clock crossing (asynchronous pulse/vld transfer) psi_common_pulse_cc.vhd link
Simple clock crossing (asynchronous data value transfer) psi_common_simple_cc.vhd link
Status clock crossing (asynchronous slow changing value transfer) psi_common_status_cc.vhd link
Synchronous CDC with AXI-S handshaking from Lower clock to Higher multiple integer clock frequency psi_common_sync_cc_n2xn.vhd link
Synchronous CDC with AXI-S handshaking from Higher clock to lower multiple integer clock frequency psi_common_sync_cc_xn2n.vhd link
Bit CDC psi_common_bit_cc.vhd link
Other components that can be used as cdc

Conversions components

Component Source Description
Data width conversion from a N-bits to a multiple N-bits psi_common_wconv_n2xn.vhd link
Data width conversion from a multiple N-bits to a N-bits psi_common_wconv_x2nn.vhd link

Time Division Multiplexing (TDM) data Handling components

Component Source Description
TDM data to parallel psi_common_tdm_par.vhd link
Parallel to TDM data psi_common_par_tdm.vhd link
TDM data to Parallel with configurable valid output channel number psi_common_tdm_par_cfg.vhd link
TDM data multiplexer psi_common_tdm_mux.vhd link
Parallel to TDM with configurable valid output output channel psi_common_par_tdm_cfg.vhd link
TDM data to parallel with last support and completion psi_common_tdm_par_fill.vhd link

Arbiters components

Component Source Description
Priority psi_common_arb_priority.vhd link
Round robin psi_common_arb_round_robin.vhd link

Interfaces components

Package Source Description
SPI master psi_common_spi_master.vhd link
SPI master configurable width psi_common_spi_master_cfg.vhd link
I2C master psi_common_i2c_master.vhd link
AXI master Simple psi_common_axi_master_simple.vhd link
AXI master Full psi_common_axi_master_full.vhd link
AXI slave IP (32 bits) psi_common_axi_slave_ipif.vhd link
AXI slave IP (64 bits) psi_common_axi_slave_ipif64.vhd N.A
AXI multi pipeline stage psi_common_axi_multi_pl_stage.vhd N.A
AXI slave Lite IP psi_common_axilite_slave_ipif.vhd link

miscellaneous components

Component Source Description
Delay settable via generics psi_common_delay.vhd link
Pipeline stage psi_common_pl_stage.vhd link
Multi pipeline stage psi_common_multi_pl_stage.vhd link
Sizable Ping pong buffer // & tdm (interface to stream continuously data into DPRAM) psi_common_ping_pong.vhd link
Delay settable via register psi_common_delay_cfg.vhd link
Generic Watchdog psi_common_watchdog.vhd link
Don't optimize (Xilinx) allows evaluating synthesis psi_common_dont_opt.vhd link
Generic Debouncer psi_common_debouncer.vhd link
Analog Trigger Generator psi_common_trigger_analog.vhd link
Digital Trigger Generator psi_common_trigger_digital.vhd link
Dynamic Shifter psi_common_dyn_sft.vhd link
Pulse/Ramp generator psi_common_ramp_gene.vhd link
Pulse generator ctrl static psi_common_pulse_generator_ctrl_static.vhd link
Parallel to serial psi_common_par_ser.vhd link
Serial to parallel psi_common_ser_par.vhd link
Find Min Max psi_common_find_min_max.vhd link
Min Max Sum psi_common_find_min_max.vhd link
PRBS psi_common_prbs.vhd link
PWM psi_common_pwm.vhd link
Sample Rate Converter - no filter psi_common_sample_rate_converter.vhd link

Packages

Package Source
Math psi_common_math_pkg.vhd
array psi_common_array_pkg.vhd
logic psi_common_logic_pkg.vhd
AXI psi_common_axi_pkg.vhd