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Merge pull request #434 from paulscottrobson/sweetasm
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Assembler in BASIC for Sweet 16
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paulscottrobson authored Apr 9, 2024
2 parents 15802e3 + 2a58a7d commit eb7b3cc
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Showing 14 changed files with 382 additions and 19 deletions.
1 change: 0 additions & 1 deletion basic/scripts/opcodes.py
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Expand Up @@ -75,7 +75,6 @@
CA dex 4
d8 cld 4
da phx 4
db stp 4
e8 inx 4
EA nop 4
f8 sed 4
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2 changes: 1 addition & 1 deletion basic/sources/arithmetic/term.asm
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Expand Up @@ -51,7 +51,7 @@ _ETKeyword:
_ETShiftUnary:
iny ; get the shifted value
lda (codePtr),y
cmp #$D0 ; not a unary function
cmp #$E0 ; not a unary function
bcc _ETSyntax
phx
asl a ; access address to jump
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Expand Up @@ -109,8 +109,11 @@ AssembleGroup3:

jsr AccessParameters ; get and output opcode
jsr AssemblerWriteByte
jsr CalculateOperand ; get a 16 bit operand
;
jsr CalculateOperand ; get a 16 bit operand
;
; Assemble a relative branch.
;
AssembleRelativeBranch:
lda XSNumber0 ; calculate the offset
sec
sbc VariableP
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232 changes: 232 additions & 0 deletions basic/sources/assembler/sweet/opcodes.asm
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; ************************************************************************************************
; ************************************************************************************************
;
; Name: opcodes.asm
; Purpose: Opcode handling code
; Created: 9th April 2024
; Reviewed: No
; Author: Paul Robson ([email protected])
;
; ************************************************************************************************
; ************************************************************************************************

.section code

; ************************************************************************************************
;
; Support Macros
;
; ************************************************************************************************

;
; Single register operand
;
sweetreg .macro
jsr SweetAsmGetRegister
ora #\1
jsr AssemblerWriteByte
.endm
;
; Single byte opcodes.
;
sweetopc .macro
lda #\1
jsr AssemblerWriteByte
.endm
;
; Short branch like 65C02
;
sweetbra .macro
lda #\1
bra ShortBranchCommon
.endm
;
; Check @ follows. May soften ?
;
checkat .macro
lda #KWD_AT
jsr ERRCheckA
.endm

; ************************************************************************************************
;
; Standard dispatcher
;
; ************************************************************************************************

; ************************************************************************************************
; SET n,<constant>
; ************************************************************************************************

SweetAsm_SET: ;; [SET]
.sweetreg $10 ; $10+x
jsr ERRCheckComma
ldx #0
jsr EXPEvalInteger16 ; operand
lda XSNumber0,x ; output it
jsr AssemblerWriteByte
lda XSNumber1,x
jsr AssemblerWriteByte
rts

; ************************************************************************************************
; <Opcode> n
; ************************************************************************************************

SweetAsm_LD: ;; [LD]
jsr SweetAsmGetAltRegister
clc
adc #$20
jsr AssemblerWriteByte
rts

SweetAsm_ST: ;; [ST]
jsr SweetAsmGetAltRegister
clc
adc #$30
jsr AssemblerWriteByte
rts

SweetAsm_LDD: ;; [LDD]
.checkat
.sweetreg $50
rts

SweetAsm_STD: ;; [STD]
.checkat
.sweetreg $70
rts

SweetAsm_POP: ;; [POP]
.checkat
.sweetreg $80
rts

SweetAsm_STP: ;; [STP]
.checkat
.sweetreg $90
rts

SweetAsm_ADD: ;; [ADD]
.sweetreg $A0
rts

SweetAsm_SUB: ;; [SUB]
.sweetreg $B0
rts

SweetAsm_POPD: ;; [POPD]
.checkat
.sweetreg $C0
rts

SweetAsm_CPR: ;; [CPR]
.sweetreg $D0
rts

SweetAsm_INR: ;; [INR]
.sweetreg $E0
rts

SweetAsm_DCR: ;; [DCR]
.sweetreg $F0
rts

; ************************************************************************************************
; No operand
; ************************************************************************************************

SweetAsm_RTN: ;; [RTN]
.sweetopc $00
rts

SweetAsm_RS: ;; [RS]
.sweetopc $0B
rts


; ************************************************************************************************
; 8 bit relative branch
; ************************************************************************************************

SweetAsm_BR: ;; [BR]
.sweetbra $01

SweetAsm_BNC: ;; [BNC]
.sweetbra $02

SweetAsm_BC: ;; [BC]
.sweetbra $03

SweetAsm_BP: ;; [BP]
.sweetbra $04

SweetAsm_BM: ;; [BM]
.sweetbra $05

SweetAsm_BZ: ;; [BZ]
.sweetbra $06

SweetAsm_BNZ: ;; [BNZ]
.sweetbra $07

SweetAsm_BM1: ;; [BM1]
.sweetbra $08

SweetAsm_BNM1: ;; [BNM1]
.sweetbra $09

SweetAsm_BK: ;; [BK]
.sweetbra $0A
;
; Branch common
;
ShortBranchCommon:
jsr AssemblerWriteByte ; output opcode
ldx #0 ; target address
jsr EXPEvalInteger16
jsr AssembleRelativeBranch ; use 65C02 code.
rts

; ************************************************************************************************
; 16 bit relative subroutine call (added)
; ************************************************************************************************

SweetAsm_BS: ;; [BS]
.sweetopc $0D ; subroutine call

ldx #0 ; target address
jsr EXPEvalInteger16

sec ; calculate target - P
lda XSNumber0
sbc VariableP
pha
lda XSNumber1
sbc VariableP+1
tax
pla ; in X:A

sec ; sub 2, 2 further back to allow for operand.
sbc #2
php
jsr AssemblerWriteByte ; low offset
plp
txa
sbc #0
jsr AssemblerWriteByte ; high offset

rts

.send code

; ************************************************************************************************
;
; Changes and Updates
;
; ************************************************************************************************
;
; Date Notes
; ==== =====
;
; ************************************************************************************************
56 changes: 56 additions & 0 deletions basic/sources/assembler/sweet/operands.asm
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; ************************************************************************************************
; ************************************************************************************************
;
; Name: operands.asm
; Purpose: Operands handling
; Created: 9th April 2024
; Reviewed: No
; Author: Paul Robson ([email protected])
;
; ************************************************************************************************
; ************************************************************************************************

.section code

; ************************************************************************************************
;
; Get a single register to A
;
; ************************************************************************************************

SweetAsmGetRegister:
jsr EXPEvalInteger8
cmp #16
bcs _SAGRRange
rts
_SAGRRange:
.error_range

; ************************************************************************************************
;
; Get a single register to A n or @an
;
; ************************************************************************************************

SweetAsmGetAltRegister:
lda (codePtr),y ; check @x
cmp #KWD_AT
bne SweetAsmGetRegister ; just normal register

iny ; consume @
jsr SweetAsmGetRegister ; get register
ora #$20 ; indirect adjust
rts

.send code

; ************************************************************************************************
;
; Changes and Updates
;
; ************************************************************************************************
;
; Date Notes
; ==== =====
;
; ************************************************************************************************
2 changes: 1 addition & 1 deletion basic/sources/commands/base/run.asm
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Expand Up @@ -140,7 +140,7 @@ Command_Shift1_Handler: ;; [!!sh1]

Command_Shift2_Handler: ;; [!!sh2]
lda (codePtr),y ; get token shifted
cmp #$D0 ; D0 up are unary functions
cmp #$E0 ; E0 up are unary functions
bcs _CS2Fail
iny
asl a ; double into X
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54 changes: 40 additions & 14 deletions basic/test.bsc
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@@ -1,16 +1,42 @@
'
' BASIC Mouse cursor manipulation
' Assembler pair test
'
mouse show
mouse to 260,180
repeat
b = mouse(x,y,s)
print chr$(20);x;" ";y;" ";b;" ";s;" "
until false
end
'
proc send.message(g,f)
while peek($FF00):wend
poke $FF01,f:poke $FF00,g
while peek($FF00):wend
endproc
mem = alloc(512)
for pass = 0 to 1
p = mem
o = pass * 3

rs
rtn

set 5,32767
ld 11
st 12
ld @13
st @14

ldd @1
std @2
pop @3
stp @4
add 5
sub 6
popd @10
cpr 7
inr 8
dcr 9

br p1
bnc p1
.p1
bc p1
bp p1
bm p1
bz p1
bnz p1
bm1 p1
bnm1 p1
bs p1
bs p2
.p2
next
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