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soft reset aurora cores instead of resetting fpgas #38

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soft reset aurora cores instead of resetting fpgas #38

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2 changes: 1 addition & 1 deletion eval/eval.ipynb
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
"metadata": {},
"outputs": [],
"source": [
"file = \"latency_tests.csv\""
"file = \"soft_reset_tests.csv\""
]
},
{
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3 changes: 3 additions & 0 deletions eval/soft_reset_tests.csv
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10 changes: 10 additions & 0 deletions host/host_aurora_hls_test.cpp
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Expand Up @@ -748,6 +748,16 @@ int main(int argc, char *argv[])
Aurora aurora;
if (!emulation) {
aurora = Aurora(instance, device, xclbin_uuid);

// soft reset aurora cores
MPI_Barrier(MPI_COMM_WORLD);
aurora.set_reset(true);
MPI_Barrier(MPI_COMM_WORLD);
std::this_thread::sleep_for(std::chrono::seconds(1));
MPI_Barrier(MPI_COMM_WORLD);
aurora.set_reset(false);
MPI_Barrier(MPI_COMM_WORLD);

check_core_status_global(aurora, config.timeout_ms, world_rank, world_size);
if (!aurora.has_framing()) {
config.frame_size = 0;
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2 changes: 0 additions & 2 deletions scripts/run_N1.sh
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Expand Up @@ -11,8 +11,6 @@ then
source env.sh
fi

srun -n 1 ./scripts/reset.sh

#https://pc2.github.io/fpgalink-gui/index.html?import=%20--fpgalink%3Dn00%3Aacl0%3Ach0-n00%3Aacl0%3Ach0%20--fpgalink%3Dn00%3Aacl0%3Ach1-n00%3Aacl0%3Ach1%20--fpgalink%3Dn00%3Aacl1%3Ach0-n00%3Aacl1%3Ach0%20--fpgalink%3Dn00%3Aacl1%3Ach1-n00%3Aacl1%3Ach1%20--fpgalink%3Dn00%3Aacl2%3Ach0-n00%3Aacl2%3Ach0%20--fpgalink%3Dn00%3Aacl2%3Ach1-n00%3Aacl2%3Ach1
srun -n 1 changeFPGAlinksXilinx --fpgalink=n00:acl0:ch0-n00:acl0:ch0 --fpgalink=n00:acl0:ch1-n00:acl0:ch1 --fpgalink=n00:acl1:ch0-n00:acl1:ch0 --fpgalink=n00:acl1:ch1-n00:acl1:ch1 --fpgalink=n00:acl2:ch0-n00:acl2:ch0 --fpgalink=n00:acl2:ch1-n00:acl2:ch1

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2 changes: 0 additions & 2 deletions scripts/run_N1_over_framesizes.sh
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Expand Up @@ -14,12 +14,10 @@ fi
#https://pc2.github.io/fpgalink-gui/index.html?import=%20--fpgalink%3Dn00%3Aacl0%3Ach0-n00%3Aacl0%3Ach0%20--fpgalink%3Dn00%3Aacl0%3Ach1-n00%3Aacl0%3Ach1%20--fpgalink%3Dn00%3Aacl1%3Ach0-n00%3Aacl1%3Ach0%20--fpgalink%3Dn00%3Aacl1%3Ach1-n00%3Aacl1%3Ach1%20--fpgalink%3Dn00%3Aacl2%3Ach0-n00%3Aacl2%3Ach0%20--fpgalink%3Dn00%3Aacl2%3Ach1-n00%3Aacl2%3Ach1
srun -n 1 changeFPGAlinksXilinx --fpgalink=n00:acl0:ch0-n00:acl0:ch0 --fpgalink=n00:acl0:ch1-n00:acl0:ch1 --fpgalink=n00:acl1:ch0-n00:acl1:ch0 --fpgalink=n00:acl1:ch1-n00:acl1:ch1 --fpgalink=n00:acl2:ch0-n00:acl2:ch0 --fpgalink=n00:acl2:ch1-n00:acl2:ch1

srun -n 1 ./scripts/reset.sh

srun -n 6 -l ./host_aurora_hls_test -p aurora_hls_test_hw_streaming.xclbin -f 0 $@

for frame_size in 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 262144 524288 1048576 2097152 4194304
do
srun -n 1 ./scripts/reset.sh
srun -n 6 -l ./host_aurora_hls_test -p aurora_hls_test_hw.xclbin -f $frame_size $@
done
6 changes: 0 additions & 6 deletions scripts/run_N2.sh
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Expand Up @@ -8,22 +8,16 @@

source env.sh

srun -n 2 --spread-job ./scripts/reset.sh

#https://pc2.github.io/fpgalink-gui/index.html?import=%20-N%202%20--fpgalink%3Dn01%3Aacl1%3Ach0-n01%3Aacl1%3Ach1%20--fpgalink%3Dn00%3Aacl2%3Ach0-n00%3Aacl2%3Ach1%20--fpgalink%3Dn00%3Aacl0%3Ach0-n00%3Aacl0%3Ach1%20--fpgalink%3Dn00%3Aacl1%3Ach0-n00%3Aacl1%3Ach1%20--fpgalink%3Dn01%3Aacl0%3Ach0-n01%3Aacl0%3Ach1%20--fpgalink%3Dn01%3Aacl2%3Ach0-n01%3Aacl2%3Ach1
changeFPGAlinksXilinx --fpgalink=n01:acl1:ch0-n01:acl1:ch1 --fpgalink=n00:acl2:ch0-n00:acl2:ch1 --fpgalink=n00:acl0:ch0-n00:acl0:ch1 --fpgalink=n00:acl1:ch0-n00:acl1:ch1 --fpgalink=n01:acl0:ch0-n01:acl0:ch1 --fpgalink=n01:acl2:ch0-n01:acl2:ch1

srun -n 12 -l ./host_aurora_hls_test $@

srun -n 2 --spread-job ./scripts/reset.sh

#https://pc2.github.io/fpgalink-gui/index.html?import=%20--fpgalink%3Dn00%3Aacl2%3Ach0-n01%3Aacl2%3Ach0%20--fpgalink%3Dn00%3Aacl1%3Ach0-n01%3Aacl1%3Ach0%20--fpgalink%3Dn00%3Aacl0%3Ach0-n01%3Aacl0%3Ach0%20--fpgalink%3Dn00%3Aacl0%3Ach1-n01%3Aacl0%3Ach1%20--fpgalink%3Dn00%3Aacl1%3Ach1-n01%3Aacl1%3Ach1%20--fpgalink%3Dn00%3Aacl2%3Ach1-n01%3Aacl2%3Ach1
changeFPGAlinksXilinx --fpgalink=n00:acl2:ch0-n01:acl2:ch0 --fpgalink=n00:acl1:ch0-n01:acl1:ch0 --fpgalink=n00:acl0:ch0-n01:acl0:ch0 --fpgalink=n00:acl0:ch1-n01:acl0:ch1 --fpgalink=n00:acl1:ch1-n01:acl1:ch1 --fpgalink=n00:acl2:ch1-n01:acl2:ch1

srun -n 12 -l ./host_aurora_hls_test $@

srun -n 2 --spread-job ./scripts/reset.sh

#https://pc2.github.io/fpgalink-gui/index.html?import=%20--fpgalink%3Dn00%3Aacl0%3Ach1-n00%3Aacl1%3Ach0%20--fpgalink%3Dn00%3Aacl0%3Ach0-n01%3Aacl0%3Ach0%20--fpgalink%3Dn00%3Aacl1%3Ach1-n01%3Aacl1%3Ach1%20--fpgalink%3Dn01%3Aacl1%3Ach0-n00%3Aacl2%3Ach0%20--fpgalink%3Dn00%3Aacl2%3Ach1-n01%3Aacl2%3Ach1%20--fpgalink%3Dn01%3Aacl2%3Ach0-n01%3Aacl0%3Ach1
changeFPGAlinksXilinx --fpgalink=n00:acl0:ch1-n00:acl1:ch0 --fpgalink=n00:acl0:ch0-n01:acl0:ch0 --fpgalink=n00:acl1:ch1-n01:acl1:ch1 --fpgalink=n01:acl1:ch0-n00:acl2:ch0 --fpgalink=n00:acl2:ch1-n01:acl2:ch1 --fpgalink=n01:acl2:ch0-n01:acl0:ch1

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