FlattenedModule no longer needs RefCell

src/ast.rs

@@ -2,7 +2,7 @@
 
 use crate::{tokenizer::{TokenTypeIdx, get_token_type_name}, linker::{NamedUUID, FileUUID}, flattening::FlattenedModule, arena_alloc::{UUIDMarker, UUID, FlatAlloc}, instantiation::InstantiationList, value::Value};
 use core::ops::Range;
-use std::{fmt::Display, cell::RefCell};
+use std::fmt::Display;
 
 // Token span. Indices are INCLUSIVE
 #[derive(Clone,Copy,Debug,PartialEq,Eq)]
@@ -154,22 +154,21 @@ pub struct Module {
     pub outputs_start : usize,
     pub code : CodeBlock,
 
-    pub flattened : RefCell<FlattenedModule>,
+    pub flattened : FlattenedModule,
 
     pub instantiations : InstantiationList
 }
 
 impl Module {
     pub fn print_flattened_module(&self) {
         println!("Interface:");
-        let flattened_borrow = self.flattened.borrow();
-        for (port_idx, port) in flattened_borrow.interface_ports.iter().enumerate() {
-            let port_direction = if port_idx < flattened_borrow.outputs_start {"input"} else {"output"};
+        for (port_idx, port) in self.flattened.interface_ports.iter().enumerate() {
+            let port_direction = if port_idx < self.flattened.outputs_start {"input"} else {"output"};
             let port_name = &self.declarations[self.ports[port_idx]].name;
             println!("    {port_direction} {port_name} -> {:?}", *port);
         }
         println!("Instantiations:");
-        for (id, inst) in &flattened_borrow.instantiations {
+        for (id, inst) in &self.flattened.instantiations {
             println!("    {:?}: {:?}", id, inst);
         }
     }

src/codegen_fallback.rs

@@ -56,10 +56,9 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
     assert!(!instance.errors.did_error.get(), "Module cannot have experienced an error");
     let mut program_text : String = format!("module {}(\n\tinput clk, \n", md.link_info.name);
     let submodule_interface = instance.interface.as_ref().unwrap();
-    let flattened_borrow = md.flattened.borrow();
     for (port_idx, real_port) in submodule_interface.iter().enumerate() {
         let wire = &instance.wires[*real_port];
-        program_text.push_str(if port_idx < flattened_borrow.outputs_start {"\tinput"} else {"\toutput /*mux_wire*/ reg"});
+        program_text.push_str(if port_idx < md.flattened.outputs_start {"\tinput"} else {"\toutput /*mux_wire*/ reg"});
         program_text.push_str(&typ_to_verilog_array(&wire.typ));
         program_text.push(' ');
         program_text.push_str(&wire.name);
@@ -68,7 +67,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
     program_text.push_str(");\n");
 
     for (_id, w) in &instance.wires {
-        if let Instantiation::WireDeclaration(wire_decl) = &flattened_borrow.instantiations[w.original_wire] {
+        if let Instantiation::WireDeclaration(wire_decl) = &md.flattened.instantiations[w.original_wire] {
             // Don't print named inputs and outputs, already did that in interface
             match wire_decl.identifier_type {
                 IdentifierType::Input | IdentifierType::Output => {continue;}

src/dev_aid/syntax_highlighting.rs

@@ -119,12 +119,11 @@ fn walk_name_color(all_objects : &[NamedUUID], links : &Links, result : &mut [ID
         let object = &links.globals[*obj_uuid];
         match object {
             Named::Module(module) => {
-                let flattened = module.flattened.borrow();
-                for (_id, item) in &flattened.instantiations {
+                for (_id, item) in &module.flattened.instantiations {
                     match item {
                         Instantiation::Wire(w) => {
                             if let &WireSource::WireRead{from_wire} = &w.source {
-                                let decl = flattened.instantiations[from_wire].extract_wire_declaration();
+                                let decl = module.flattened.instantiations[from_wire].extract_wire_declaration();
                                 if decl.identifier_type == IdentifierType::Virtual {continue;} // Virtual wires don't appear in the program text
                                 result[w.span.assert_is_single_token()].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
                             }
@@ -135,7 +134,7 @@ fn walk_name_color(all_objects : &[NamedUUID], links : &Links, result : &mut [ID
                             result[name_token].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
                         }
                         Instantiation::Connection(conn) => {
-                            let decl = flattened.instantiations[conn.to.root].extract_wire_declaration();
+                            let decl = module.flattened.instantiations[conn.to.root].extract_wire_declaration();
                             if decl.identifier_type == IdentifierType::Virtual {continue;} // Virtual wires don't appear in the program text
                             result[conn.to.span.0].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
                         }

src/flattening.rs

@@ -255,7 +255,7 @@ impl<'l, 'm> FlatteningContext<'l, 'm> {
 
         let submodule_local_wires = func_instantiation.local_wires.clone();
 
-        let (inputs, output_range) = md.flattened.borrow().func_call_syntax_interface();
+        let (inputs, output_range) = md.flattened.func_call_syntax_interface();
 
         let mut args = &func_and_args[1..];
 

src/linker.rs

@@ -342,7 +342,7 @@ impl Linker {
     fn get_flattening_errors(&self, file_uuid : FileUUID, errors : &ErrorCollector) {
         for v in &self.files[file_uuid].associated_values {
             if let Named::Module(md) = &self.links.globals[*v] {
-                errors.ingest(&md.flattened.borrow().errors);
+                errors.ingest(&md.flattened.errors);
                 md.instantiations.collect_errors(errors);
             }
         }
@@ -526,23 +526,16 @@ impl Linker {
 
             println!("Flattening {}", md.link_info.name);
 
-            let flattened = FlattenedModule::initialize(&self, md, !md.link_info.is_fully_linked);
+            let mut flattened = FlattenedModule::initialize(&self, md, !md.link_info.is_fully_linked);
+            println!("Typechecking {}", &md.link_info.name);
+            flattened.typecheck(self);
+            flattened.find_unused_variables();
 
             let Named::Module(md) = &mut self.links.globals[*id] else {unreachable!()};
-            *md.flattened.get_mut() = flattened;
+            md.flattened = flattened;
             md.instantiations.clear_instances();
         }
 
-        // Then do proper flattening on every module
-        for id in &module_ids {
-            let Named::Module(md) = &self.links.globals[*id] else {unreachable!()};
-            println!("Typechecking {}", &md.link_info.name);
-
-            let mut flattened_mut_borrow = md.flattened.borrow_mut();
-            flattened_mut_borrow.typecheck(self);
-            flattened_mut_borrow.find_unused_variables();
-        }
-
         // Can't merge these loops, because instantiation can only be done once all modules have been type checked
         for (id, named_object) in &self.links.globals {
             if let Named::Module(md) = named_object {
@@ -557,7 +550,6 @@ impl Linker {
         let Named::Module(md) = &self.links.globals[module_id] else {panic!("{module_id:?} is not a Module!")};
         println!("Instantiating {}", md.link_info.name);
 
-        let flattened = md.flattened.borrow();
-        md.instantiations.instantiate(&md.link_info.name, &flattened, self)
+        md.instantiations.instantiate(&md.link_info.name, &md.flattened, self)
     }
 }

src/parser.rs

@@ -3,7 +3,7 @@ use num::BigInt;
 
 use crate::{tokenizer::*, errors::*, ast::*, linker::FileUUID, flattening::FlattenedModule, arena_alloc::FlatAlloc, instantiation::InstantiationList, value::Value};
 
-use std::{iter::Peekable, str::FromStr, ops::Range, cell::RefCell};
+use std::{iter::Peekable, str::FromStr, ops::Range};
 use core::slice::Iter;
 
 use std::mem::replace;
@@ -725,7 +725,7 @@ impl<'g, 'file> ASTParserContext<'g, 'file> {
             global_references : replace(&mut self.global_references, Vec::new()),
             is_fully_linked : false
         };
-        Some(Module{declarations, ports, outputs_start, code, link_info, flattened : RefCell::new(FlattenedModule::empty(self.errors.file)), instantiations : InstantiationList::new()})
+        Some(Module{declarations, ports, outputs_start, code, link_info, flattened : FlattenedModule::empty(self.errors.file), instantiations : InstantiationList::new()})
     }
 
     fn parse_ast(mut self, outer_token_iter : &mut TokenStream) -> ASTRoot {